Embedded Complex Floating Point Hardware Accelerator

Ghasemazar, Amin; Goli, Mehran; Afzali-Kusha, Ali

doi:10.1109/vlsid.2014.61

Cited by 5 publications

(5 citation statements)

References 5 publications

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“…In a conventional NoC, the theoretical send latency can be estimated roughly from the following equation: 2 (1) In which, n is the minimum number of links between the two cores. Now the NOC latency can be calculated for our proposed method similarly: 2 (2) Where K represents the number of times that a packet passes through the bisection bandwidth. Because there are two rows of switches in the bisection, there will be extra latency associated with more switches.…”

Section: Proposed Noc Architecturementioning

confidence: 99%

“…Application specific design provides the minimum latency and power for running an application by customizing the design to optimally fit the application; hence we choose to use it, instead of general processing units. On the other hand, these configurable elements can be used to map customized accelerating hardwares, as suggested in [2,3], or approximated processing units, as shown in [4], for a specific use which results in reduction in application runtime. Another benefit of this re-configurability, is the displacement for core mapping.…”

Section: Introductionmentioning

confidence: 99%

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Application-specific power-aware mapping for reconfigurable NoC architectures

Goli

Ghasemazar

Navabi

2015

2015 10th International Conference on Design &Amp; Technology of Integrated Systems in Nanoscale Era (DTIS)

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In this paper, we propose a new topology-core reconfigurable architecture for network-on-chips (NoC). The majority of existing research on reconfigurable architectures is focused on either reconfiguring topology of NoC or reconfiguring processing elements of the network. Our approach uses a hybrid algorithm to take advantages of both these methods by using field programmable gate array (FPGA) as reconfigurable processing elements. Moreover, programmable switches among routers are applied for topology reconfigurability. The experimental results show extensive improvement over the state-of-the-art research in terms of power consumption, network performance and application execution time.

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Section: Proposed Noc Architecturementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Application-specific power-aware mapping for reconfigurable NoC architectures

Goli

Ghasemazar

Navabi

2015

2015 10th International Conference on Design &Amp; Technology of Integrated Systems in Nanoscale Era (DTIS)

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“…The field programmable gate array (FPGA) is more flexible in programming than CPLD; the programming method of CPLD is to modify the logic function with fixed internal circuit, and the programming mode of FPGA is mainly to change the wiring of internal connections; CPLD has more advantages on completing various algorithms and combinational logic and FPGA is more suitable for tasks that require higher timing logic; therefore, FPGA is more suitable than CPLD for the design of LCD controller with relatively high timing requirements. In addition, due to the properties of open structure, parallel processing design with FPGA is possible and easily designed [2][3][4]. It describes the design and implementation of a multi-function LCD controller based on FPGA, introduces the overall structure of the controller, and then describes in detail the design and implementation methods of each module and the pivotal technologies involved [2].…”

Section: Introductionmentioning

confidence: 99%

The Design of IP Core for LCD Controller Based on SOPC

Zhou

Guo

2018

MATEC Web Conf.

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In this paper, it introduces the design and implementation of custom IP core for liquid crystal display (LCD) controller based on system on a programmable chip (SOPC) technology and Verilog hardware description language (HDL). The IP core can be put up as a general-purpose peripheral module to the Avalon Bus, communicating with the NIOS II through registers, and the underlying sequential logic for communicating with the external LCD liquid crystal module is automatically completed by the module. The driver does not need to care about the details of the underlying timing, it only needs to implement the read and write operations of the LCD data through register access, thus achieve the purpose of controlling the display content of the LCD. In addition to reducing the complexity of driver development, the design can also take full advantage of the parallel operation of hardware logic to improve the execution efficiency of the entire system and the throughput of processing tasks, especially in some occasions where high-speed image real-time processing is required. Simulations and experiments show that the IP core for LCD controller has good stability, versatility and compatibility.

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“…It could also be programmed as an ASIC chip, which combines many functions into one FPGA chip, such as PID controller, velocity profile generation, interpolator, and data conversion [5]. It is also used to speed up the mathematic calculation and greatly enhance the performance of the motion planning and drive design [6][7][8], or used on the other relative field where hardware calculation is important. In addition, due to the properties of open structure, parallel processing design with FPGA is possible and easily designed [7,9].…”

Section: Introductionmentioning

confidence: 99%

“…It is also used to speed up the mathematic calculation and greatly enhance the performance of the motion planning and drive design [6][7][8], or used on the other relative field where hardware calculation is important. In addition, due to the properties of open structure, parallel processing design with FPGA is possible and easily designed [7,9]. Besides, some IPs of soft code processor for system on a chip (SOC) design are provided, such as the MCU NIOS II, Arduino, or ARM DSP [2][3][4][10][11][12][13], which could be adopted to easily realize the design of embedded system, or design in co-processor operation.…”

Section: Introductionmentioning

confidence: 99%

An FPGA-Based Multiple-Axis Velocity Controller and Stepping Motors Drives Design

2016

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Abstract.A Field Programmable Gate Array based system is a great hardware platform to support the implementation of hardware controllers such as PID controller and fuzzy controller. It is also programmed as hardware accelerator to speed up the mathematic calculation and greatly enhance the performance as applied to motor drive and motion control. Furthermore, the open structure of FPGA-based system is suitable for those designs with the ability of parallel processing or soft code processor embedded. In this paper, we apply the FPGA to a multi-axis velocity controller design. The developed system integrated three functions inside the FPGA chip, which are respectively the stepping motor drive, the multi-axis motion controller and the motion planning. Furthermore, an embedded controller with a soft code processor compatible to 8051 micro-control unit (MCU) is built to handle the data transfer between the FPGA board and host PC. The MCU is also used to initialize the motion control and run the interpolator. The designed system is practically applied to a XYZ motion platform which is driven by stepping motors to verify its performance.

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Embedded Complex Floating Point Hardware Accelerator

Cited by 5 publications

References 5 publications

Application-specific power-aware mapping for reconfigurable NoC architectures

Application-specific power-aware mapping for reconfigurable NoC architectures

The Design of IP Core for LCD Controller Based on SOPC

An FPGA-Based Multiple-Axis Velocity Controller and Stepping Motors Drives Design

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