Embedded Devices Security: Design and Implementation of a Light RDBMS Encryption Utilizing Multi-Core Processors

Abstract

The pervasive proliferation of embedded, mobile, and IoT devices continue to change our lifestyle dramatically. However, the huge increase in these devices has come with critical breaches to data resting inside them. Many types of such data are considered to be sensitive and confidential. Because the most sensitive data of such devices are resting in databases, focusing on encrypting SQLite databases will be more efficient than full disk encryption (FDE). While SQLite is a very popular, lightweight, and easy-to-use relational database suitable for embedded and mobile devices, its stored data suffers serious security risks. If an attacker can gain access to higher system privileges or find a way to access the database plain file, he can tamper with the database files and user-sensitive data, which breaches the security CIA triad of SQLite. To ensure data confidentiality in SQLite databases of embedded devices, we present a design and implementation of a parallel database encryption system, called SQLite-XTS. The developed system encrypts the database pages on-the-fly in a transparent manner without user intervention. Because performance is a critical issue, SQLite-XTS utilizes multi-core processors coming with most current mobile and embedded devices. The developed parallel SQLite-XTS was successfully implemented and integrated into a testbed device. To assess the performance and feasibility of this system, it was compared to three other SQLite implementations: plain SQLite, serial XTS SQLite, and SQLCipher-CBC. The results show that SQLite-XTS reduces the overhead of database encryption from 30.8% with serial implementation to 17.8% when SQLite-XTS is used. This provides the developed system with an efficiency of 73% compared with its serial counterpart. The results clarify that SQLite-XTS introduces significant performance improvements compared to other implementations. Experiments also show that the system has a very low impact on the memory of these resource-limited devices.

“Interrupting” the Status Quo: A First Glance at the RISC-V Advanced Interrupt Architecture (AIA)

“…The evaluation was conducted using a single-core CVA6-based SoC (@50 MHz), with the RISC-V hypervisor extension, on a Genesys 2 FPGA board. The software stack includes OpenSBI (version 1.1), Bao hypervisor (version 1.0) [25], [26], and Linux (version 6.1-rc4). Bao and OpenSBI were compiled using SiFive's GCC version 10.1.0 for riscv64 unknown targets, and Linux was compiled using GNU RISC-V GCC version 10.3.0 for riscv64 Linux targets.…”

A Review Method for Analysis of the Causes of Data Breach in the Pasca Pandemic

“…Kemajuan yang dipercepat dalam komunikasi, jaringan, dan teknologi informasi membentuk bisnis global, dan diperkirakan akan terus mengubah struktur bisnis di masa mendatang. Perkembangan ini memiliki banyak keuntungan dan kerugian bagi semua pemangku kepentingan organisasi [1][2][3]. Manajemen sistem informasi semakin mempertimbangkan keamanan dan privasi informasi karena potensi masalah yang dapat mengancam keamanan data informasi.…”