Embedded DRAM in 45-nm Technology and Beyond

Anand, D.; Gorman, K.; Jacunski, Mark; Paparelli, A.

doi:10.1109/mdt.2011.2

Cited by 6 publications

(6 citation statements)

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“…For example, an RLDRAM die is reported to be 40-80% larger than a comparable DDR2 DRAM die [20]. Alternatively, the ideas of embedding DRAM into processor dies [7], embedding SRAM into DRAM dies [56], or providing multiple row buffers per DRAM bank [14,29] have been proposed, but they are more suitable for caches. Stacking DRAM dies on top of the processor die [46] can reduce main-memory access latency and power, as the physical distances and impedance between the dies are greatly reduced.…”

Section: Introductionmentioning

confidence: 99%

Reducing memory access latency with asymmetric DRAM bank organizations

Son

Seongil

et al. 2013

Proceedings of the 40th Annual International Symposium on Computer Architecture

103

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DRAM has been a de facto standard for main memory, and advances in process technology have led to a rapid increase in its capacity and bandwidth. In contrast, its random access latency has remained relatively stagnant, as it is still around 100 CPU clock cycles. Modern computer systems rely on caches or other latency tolerance techniques to lower the average access latency. However, not all applications have ample parallelism or locality that would help hide or reduce the latency. Moreover, applications' demands for memory space continue to grow, while the capacity gap between lastlevel caches and main memory is unlikely to shrink. Consequently, reducing the main-memory latency is important for application performance. Unfortunately, previous proposals have not adequately addressed this problem, as they have focused only on improving the bandwidth and capacity or reduced the latency at the cost of significant area overhead.We propose asymmetric DRAM bank organizations to reduce the average main-memory access latency. We first analyze the access and cycle times of a modern DRAM device to identify key delay components for latency reduction. Then we reorganize a subset of DRAM banks to reduce their access and cycle times by half with low area overhead. By synergistically combining these reorganized DRAM banks with support for non-uniform bank accesses, we introduce a novel DRAM bank organization with center high-aspect-ratio mats called CHARM. Experiments on a simulated chip-multiprocessor system show that CHARM improves both the instructions per cycle and system-wide energy-delay product up to 21% and 32%, respectively, with only a 3% increase in die area. Figure 1: The capacity and bandwidth of DRAM devices have increased rapidly over time, but their latency has decreased much more slowly [41].

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Section: Introductionmentioning

confidence: 99%

Reducing memory access latency with asymmetric DRAM bank organizations

Son

Seongil

et al. 2013

Proceedings of the 40th Annual International Symposium on Computer Architecture

103

View full text Add to dashboard Cite

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“…The proposed parallel architecture is presented in §2; §3 provides some background to the relevant technologies; §4 describes the implementation model; §5 presents the parameters and an analysis of the model's cost and scaling; §6 describes the experimental methodology 1 The central component of a DRAM is an array core, a two-dimensional array of cells and associated peripheral circuitry. The array core is sized to trade-o well between density and delay and energy per activation and refresh.…”

Section: Contributions and Outline Of The Papermentioning

confidence: 99%

“…The memory is typically implemented with a collection of DRAM arrays that are integrated in one or more chips and connected with an interconnect specialised to transmit control, data and address information, to provide e cient random access. 1 The architecture of a DRAM system is therefore tightly coupled but inherently distributed. In this sense, a DRAM system is conceptually similar to a distributed-memory parallel computer, which is composed of an array of processors with local memories, connected by a communication network.…”

Section: Introductionmentioning

confidence: 99%

“…Faster memories are by design less dense, with control logic overheads amortised over a smaller number of bit cells 7. As eDRAM technology has matured, the access latency has approached that of SRAM[1], especially for large memories where the ight-time across the array can dominate access latency and the improved density of eDRAM can signi cantly reduce this. Its main application has been to build large on-chip caches, replacing SRAM, for example in the BlueGene/L[18] and Power7[5] chips.…”

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Emulating a large memory with a collection of small ones

Hanlon

2012

Preprint

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Sequential computation is well understood but does not scale well with current technology. Within the next decade, systems will contain large numbers of processors with potentially thousands of processors per chip in order to deliver continuing growth in performance. Despite this, many computational problems exhibit little or no parallelism and many existing formulations are sequential. It is therefore essential that highly-parallel architectures can support sequential computation by emulating large memories with collections of smaller ones, thus supporting e cient execution of sequential programs or sequential components of parallel programs. This paper demonstrates that a realistic parallel architecture with scalable low-latency communications can execute large-memory sequential programs with a factor of only 2 to 3 overhead, when compared to a conventional sequential memory architecture. This overhead seems an acceptable price to pay to be able to switch between executing highly-parallel programs and sequential programs with large memory requirements. E cient emulation of large memories could therefore facilitate a transition from sequential machines by allowing existing programs to be compiled directly to a highly-parallel architecture and then for their performance to be improved by exploiting parallelism in memory accesses and the computation.

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“…In detail, IC devices are usually made of SiO 2 , other dielectrics, copper, etc. and have several features of around a few tens of nanometers (e.g., 45 nm in embedded dynamic random-access memories (Anand et al, 2011)), while multi-level MEMS cover a broader set of standard and non-standard materials and have a wide feature size of up to mm. When the IC-CMP is directly applied to the fabrication of multi-level MEMS, these differences in machining material and feature size aggravate the intrinsic shortcoming of the IC-CMP, which leads to the easy occurrence of local structural defects (i.e., dishing defects) and the spatially non-uniform amount of the defects (in other words, dishing amount highly sensitive to pattern width) on a polished surface.…”

Section: Introductionmentioning

confidence: 99%