2004
DOI: 10.1007/978-3-540-30205-6_40
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Embedded EEPROM Speed Optimization Using System Power Supply Resources

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“…Even if they are a fraction of the total testing time, delay overheads due to the STI could be removed. In addition, at-speed read operation on high-speed eFlash [7] could become mandatory, and is only possible with BIST. A comparison was performed on several products embedding high-speed flash memories (25ns random read access time) ranging from 32KB to 1024KB.…”
Section: Test Algorithms and Fault Coveragementioning
confidence: 99%
“…Even if they are a fraction of the total testing time, delay overheads due to the STI could be removed. In addition, at-speed read operation on high-speed eFlash [7] could become mandatory, and is only possible with BIST. A comparison was performed on several products embedding high-speed flash memories (25ns random read access time) ranging from 32KB to 1024KB.…”
Section: Test Algorithms and Fault Coveragementioning
confidence: 99%