Embedded PCM macro for automotive-grade microcontroller in 28nm FD-SOI

Disegni, F.; Annunziata, R.; Molgora, A.; Campardo, G.; Cappelletti, P.; Zuliani, P.; Ferreira, Paulo; Ventre, A.; Castagna, G.; Cathelin, Andreia; Gandolfo, A.; Goller, F; Malhi, S.D.S.; Manfre, D.; Maurelli, A.; Torti, C.; Arnaud, F.; Carfi, M.; Perroni, M.; Caruso, M.; Pezzini, Saverio; Piazza, Gero Di; Weber, O.; Peri, Maurizio

doi:10.23919/vlsic.2019.8778129

Cited by 5 publications

(5 citation statements)

References 1 publication

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“…In the last ten years, RRAM technologies have gain interest in the scientific community and are already perceived as a future eFlash technology replacement candidate by several industrials for their advanced technology node microcontrollers [7]- [9], [21], [22]. In this context, three major technology families are under investigation : [4], [23] and (iii) Chalcogenide-based Phase Change Memories (PCM) [6].…”

Section: B Rram Technologiesmentioning

confidence: 99%

“…An extremely active research field focuses on the integration of emerging nonvolatile memory technologies (usually referred as Resistive Random Access Memories or RRAM), as they enable a relatively low cost and fine grain integration with CMOS, a fast switching capability, a higher density and endurance than regular eFlash technologies [3]- [6]. All these characteristics make RRAM technologies an enabler for sub-28nm CMOS technologies microcontrollers [7]- [9] and open the path for new breakthrough memory integration, as data memory or as part of the cache hierarchy for Edge-level computing architectures [10], [11].…”

Section: Introductionmentioning

confidence: 99%

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Write Termination Circuits for RRAM: A Holistic Approach From Technology to Application Considerations

et al. 2020

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While Resistive Random Access Memories (RRAM) are perceived nowadays as a promising solution for the future of computing, these technologies suffer from intrinsic variability regarding programming voltage, switching speed and achieved resistance values. Write Termination (WT) circuits are a potential solution to solve these issues. However, previously reported WT circuits do not demonstrate sufficient reliability. In this work, we propose an industrially-ready WT circuit that was simulated with a RRAM model calibrated on real measurements. We perform extensive CMOS and RRAM variability simulations to extract the actual performances of the proposed WT circuit. Finally, we simulate the effects of the proposed WT circuit with memory traces extracted from real Edge-level data-intensive applications. Overall, we demonstrate 2× to 40× of energy gains at bit level. Moreover, we show from 1.9× to 16.2× energy gains with real applications running depending on the application memory access pattern thanks to the proposed WT circuit.INDEX TERMS RRAM, embedded memories, write termination, memory modeling, low-power design

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Section: B Rram Technologiesmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Write Termination Circuits for RRAM: A Holistic Approach From Technology to Application Considerations

et al. 2020

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“…However, RRAM technologies suffer from limited endurance, forbidding their use as computation memories, thereby calling for reasonable usage as program, data or last level cache memory. Popular technologies such as Spin-Transfer Torque Magnetic RRAM (MRAM) [9], Phase Change Memories (PCM) [10] or filamentary-based RRAM (ReRAM) [3] are under intense exploration by the scientific community and some (PCM, ReRAM) are currently being integrated in commercial microcontrollers as a replacement for eflash technologies [11], [12], [13]. However, the jump towards intensive usage has not been achieved yet, and RRAM technologies are still considered as a regular eFlash replacement.…”

Section: A Rram Technologiesmentioning

confidence: 99%

Functionality Enhanced Memories for Edge-AI Embedded Systems

Levisse

Rios

Simon

et al. 2019

2019 19th Non-Volatile Memory Technology Symposium (NVMTS)

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With the surge in complexity of edge workloads, it appeared in the scientific community that such workloads cannot be anymore overflown to the cloud due to the huge edge device to server communication energy cost and the high energy consumption induced in high end server infrastructure. In this context, edge devices must be able to efficiently process complex data-intensive workloads bringing in the concept of Edge AI. However, current architectures show poor energy efficiency while running data intensive workloads. While the community looks toward the integration of new memory architectures using emerging resistive memories and new specific accelerators, we propose a new concept to boost the energy efficiency of Edge systems running data intensive workloads : Functionality Enhanced Memories (FEM). FEM consist on a memory architecture with new functionalities at a decent area overhead cost. In this work, we demonstrate the feasibility of native transpose access for 1Transistor-1RRAM bitcells leveraging three independent gates transistors. Based on that, we thereby propose a concept of FEM-enabled Edge system embedding the proposed native transpose access RRAM-based memory architecture and an in-SRAM computing architecture (the BLADE).

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“…Beyond the well-known feature of PCM cells already demonstrated in the literature, i.e. a large resistance ratio of 10 3 , a low variability thanks to a bulk phase change (crystalline and amorphous state), a mature process, and a large endurance 10 9 [4][5][6][7], the performances of memory with OTS as selector is mainly driven by the OTS selectivity. Regarding the OTS selectivity feature, numerous papers have reported very different performances [9][13] [14], with selectivity ranging from 10 3 to 10 7 .…”

Section: Introductionmentioning

confidence: 98%

“…and dataintensive treatment, exacerbates the requirement in terms of performances and memory capacity on edge devices, such as the high-end Micro Controller Unit (MCU). In this context, highdensity memory based on emerging concept could replace actual solutions such as 1.5T NOR Flash memory or 1T1R Phase Change Memory (PCM) [1][2][3][4][5][6][7]. In this context, to decrease drastically the bit cell footprint, a back-end selector solution could be adopted.…”

Section: Introductionmentioning

confidence: 99%

A Self-referenced and regulated sensing solution for PCM with OTS selector

Gasquez

Giraud

Boivin

et al. 2021

2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SoC)

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Phase change memory (PCM) device associated with Ovonic Threshold Switch (OTS) selector is a proven solution to fill the gap between DRAM and mass storage. This technology also has the potential to be embedded in a high-end microcontroller. However, programming and reading phases efficiency is directly linked to the selector's leakage current and the sneak-path management. To tackle this challenge, we propose in this paper, a new sense amplifier able to generate an autoreference taking into account leakage current of unselected cell, including a regulation loop to compensate voltage drop due to reading current sensing. This auto-referenced sense, built on the charge-sharing principle, is designed on a 28nm FDSOI technology and validated through extensive Monte-Carlo and corner cases simulations. From the simulation results, our sense amplifier is demonstrated to be robust for an ultra-large range of sneak-path current and consequently for a large range of memory array size, suitable for embedded memory in high-end microcontroller.

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Embedded PCM macro for automotive-grade microcontroller in 28nm FD-SOI

Cited by 5 publications

References 1 publication

Write Termination Circuits for RRAM: A Holistic Approach From Technology to Application Considerations

Write Termination Circuits for RRAM: A Holistic Approach From Technology to Application Considerations

Functionality Enhanced Memories for Edge-AI Embedded Systems

A Self-referenced and regulated sensing solution for PCM with OTS selector

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