Embedded Silicon Fan‐Out (eSiFO®) Technology for Wafer‐Level System Integration

Yu, Daquan

doi:10.1002/9781119313991.ch8

Cited by 8 publications

(2 citation statements)

References 9 publications

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“…The CPU time was about 4 min for the 3.3GHz processor; difference grid in horizontal plane was 400×400. Comparison of curves 1 and 2 shows the good agreement between results from paper [9] and results calculated using Quasi-3D-Overheat tool. In Figure 11 the temperature distribution on the die is shown.…”

Section: Embedded Silicon Fan-out (Esifo) Structuresupporting

confidence: 54%

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Quasi-3D Numerical Thermal Modelling of Electronic Systems in Package

Petrosyants,

Ryabov

2024

J. Phys.: Conf. Ser.

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The technology of three-dimensional (3D) packaging currently provides an increase in the efficiency of various electronic systems, bringing the volume of the package and heat dissipation into proper correlation. For many types of modern 3D packages the electro-thermal properties were not yet investigated. So the thermal modelling of 3D system in package (SiP) constructions became obliged for package designers. The commercial universal fully-3D simulators are not effective for practical engineers because of the complexity in using. The problem-oriented method called “Quasi-3D”was proposed and software tool Quasi-3D-Overheatwas developed to save the pre- and post-processing labour and CPU time. Numerical thermal modelling for different types of modern SiP structures: bridge-chip; p2 Pack; chip stack with TSV; embedded silicon fan-out was carried out and compared with measured temperatures. Simulation error was not more than 10–15%.

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Section: Embedded Silicon Fan-out (Esifo) Structuresupporting

confidence: 54%

“…The schematic view of the considered DUT is presented in Figure 9 [9]. The main advantage of the eSiFO package is that the silicon carrier is used as the fan-out area instead of molding compound.…”

Section: Embedded Silicon Fan-out (Esifo) Structurementioning

confidence: 99%