Embedded SoC Resource Manager to Control Temperature and Data Bandwidth

Saen, Makoto; Osada, Kensuke; Misaka, Satoshi; Yamada, Takazo; Tsujimoto, Y.; Kondoh, Y.; Kamei, Takeshi; Yoshida, Yutaka; Nagahama, E.; Nitta, Yusuke; Ito, Takashi; Kameyama, Tadashi; Irie, Naohiko

doi:10.1109/isscc.2007.373411

Cited by 10 publications

(7 citation statements)

References 3 publications

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“…This Foxton technology [1] allows for dynamic voltage and frequency scaling based on sampled monitor data. A similar approach for a Hitachi multiprocessor [2] uses thermal and performance information to control voltage and bandwidth allocation. All of these systems assume small numbers of cores and monitors connected in an ad hoc fashion.…”

Section: Monitors and Related Interconnectsmentioning

confidence: 99%

A monitor interconnect and support subsystem for multicore processors

Madduri

Vadlamani

Burleson

et al. 2009

2009 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

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Abstract-In many current SoCs, the architectural interface to onchip monitors is ad hoc and inefficient. In this paper, a new architectural approach which advocates the use of a separate lowoverhead subsystem for monitors is described. A key aspect of this approach is an on-chip interconnect specifically designed for monitor data with different priority levels. The efficiency of our monitor interconnect is assessed for a multicore system using both an interconnect and a system-level simulator. Collected monitor information is used by a dedicated processor to control the frequency and voltage of individual multicore processors. Experimental results show that the new low-overhead subsystem facilitates employment of thermal and delay-aware dynamic voltage and frequency scaling.

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Section: Monitors and Related Interconnectsmentioning

confidence: 99%

A monitor interconnect and support subsystem for multicore processors

Madduri

Vadlamani

Burleson

et al. 2009

2009 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

View full text Add to dashboard Cite

show abstract

“…[8] The IEEE 1687 standard enables the ease of EIs integration, portability and reuse. On the other hand, conventional on-chip access mechanisms to EIs range from direct connections for a small number of EIs [9], reusing the functional network [10] or using a dedicated EIs network [11]. With the increasing reliability issues in nano-technologies, future SoCs will be required to periodically sense and accordingly adapt during runtime [12].…”

Section: Lists Examples Of Ras Proceduresmentioning

confidence: 99%

An On-Chip IEEE 1687 Network Controller for Reliability and Functional Safety Management of System-on-Chips

Ibrahim

Kerkhoff

2019

2019 IEEE International Test Conference in Asia (ITC-Asia)

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The IEEE 1687 standard defines a standardized mechanism for the off-chip access of embedded instruments. A subset of these instruments are also used for maintaining the reliability and functional safety of the chip during its lifetime. For example, temperature sensors, voltage monitors and Built-In-Self-Test engines. In this paper, we present a novel on-chip controller for IEEE 1687 networks which can execute instrument procedures documented in the IEEE 1687 PDL language. These procedures are incorporated within the reliability and functional safety embedded software that uses the measurements data of the instruments. The controller includes an efficient structural model of the IEEE 1687 network and can perform on-chip pattern retargeting on arbitrary networks. In addition, it can perform localization of instrument interrupts that are propagated via multi-mode IEEE 1687 networks.

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“…This Foxton technology [3] allows for dynamic voltage and frequency scaling based on sampled monitor data. A similar approach for a Hitachi multiprocessor [4] uses thermal and performance information to control voltage and bandwidth allocation. All of these systems assume small numbers of cores and monitors connected in an ad hoc fashion.…”

Section: A Monitors and Monitor Subsystemsmentioning

confidence: 99%

A Dedicated Monitoring Infrastructure for Multicore Processors

Zhao

Madduri

Vadlamani

et al. 2011

IEEE Trans. VLSI Syst.

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Abstract-On-chip monitoring of environmental information, such as temperature, voltage, and error data, is becoming increasingly important. To address this need, a low-overhead architectural approach to monitor data collection and use in multicore systems is described. A key aspect of our stand-alone monitoring subsystem is a low-complexity, on-chip network designed to transport monitor data with multiple priority levels. Collected monitor information is evaluated by a dedicated processor. Experimental results using architectural and interconnect simulators show that the new low-overhead subsystem facilitates employment of thermal and delay-aware dynamic voltage and frequency scaling. In contrast to using existing on-chip interconnect resources to communicate monitor data, the new subsystem provides necessary bandwidth for monitor data traffic without impacting application data traffic. Synthesis results show that our dedicated monitoring approach consumes about 0.2% of multicore area and power resources for an 8-core system based on AMD Athlon 64 processor cores.Index Terms-Network on chip, on-chip monitoring, multicore.

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Embedded SoC Resource Manager to Control Temperature and Data Bandwidth

Cited by 10 publications

References 3 publications

A monitor interconnect and support subsystem for multicore processors

A monitor interconnect and support subsystem for multicore processors

An On-Chip IEEE 1687 Network Controller for Reliability and Functional Safety Management of System-on-Chips

A Dedicated Monitoring Infrastructure for Multicore Processors

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