Embedded Systems Start-Up under Timing Constraints on Modern FPGAs

Abstract

In this paper we present novel techniques, methods and tool flows that enable embedded systems implemented on FPGAs to start-up under tight timing constraints (i.e., hard deadlines). Meeting the application deadline is achieved by exploiting the FPGA programmability in order to implement a two-stage system start-up approach, as well as a suitable memory hierarchy. This reduces the FPGA configuration time as well as the startup time of the embedded software. Thereby the start-up time for timing-critical parts of a design neither dependent on the complexity nor on the start-up time of the complete system. An automotive case study is used to demonstrate the feasibility and quantify the benefits of the proposed approach.

Lossless Compression Decoders for Bitstreams and Software Binaries Based on High-Level Synthesis

“…With the trend towards more complex software systems with respect to code size and the number of processors, the capacity of the external nonvolatile memory needed to store the software binaries grows accordingly. Furthermore, the required throughput for reading software binaries needs to improve in order to meet the limited start-up time of some systems [8].…”