Embedded TCP/IP Controller for a RISC-V SoC

Tsai, Chun-Jen; Lee, Yi-De

doi:10.1109/vlsi-soc54400.2022.9939600

Cited by 2 publications

(1 citation statement)

References 12 publications

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“…Table 4 shows the Artix-7 FPGA resource requirements for MicroBlaze, Cortex-M3, RISC-V, MIPS32 and HW_nMPRA_RTOS FPGA implementation architectures ( Włostowski, Serrano & Vaga, 2015 ; Li, Zhang & Bao, 2022 ; Tsai & Lee, 2022 ; Sarjoughian, Chen & Burger, 2008 ). It can be stated that the flip-flops and combinational logic requirements are convenient for the architecture proposed in this article, considering that HW_nMPRA_RTOS guarantees context switching in 1 ÷ 2 clock cycles and predictable response to interrupt events.…”

Section: Resultsmentioning

confidence: 99%

Soft-core processor integration based on different instruction set architectures and field programmable gate array custom datapath implementation

Zagan

Găitan

2023

PeerJ Computer Science

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One of the fundamental requirements of a real-time system (RTS) is the need to guarantee re-al-time determinism for critical tasks. Task execution rates, operating system (OS) overhead, and task context switching times are just a few of the parameters that can cause jitter and missed deadlines in RTS with soft schedulers. Control systems that are susceptible to jitter can be used in the control of HARD RTS as long as the cumulative value of periodicity deviation and worst-case response time is less than the response time required by that application. This artcle presents field-programmable gate array (FPGA) soft-core processors integration based on different instruction set architectures (ISA), custom central processing unit (CPU) datapath, dedicated hardware thread context, and hardware real-time operating system (RTOS) implementations. Based on existing work problems, one parameter that can negatively influence the performance of an RTS is the additional costs due to the operating system. The scheduling and thread context switching operations can significantly degrade the programming limit for RTS, where the task switching frequency is high. In parallel with the improvement of software scheduling algorithms, their implementation in hardware has been proposed and validated to relieve the processor of scheduling overhead and reduce RTOS-specific overhead.

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