Embedding CCSL into Dynamic Logic: A Logical Approach for the Verification of CCSL Specifications

Abstract

The Clock Constraint Specification Language (CCSL) is a clock-based specification language for capturing causal and chronometric constraints between events in Real-Time Embedded Systems (RTESs). Due to the limitations of the existing verification approaches, CCSL lacks a full verification support for 'unsafe CCSL specifications' and a unified proof framework. In this paper, we propose a novel verification approach based on theorem proving and SMT-checking. We firstly build a logic called CCSL Dynamic Logic (CDL), which extends the traditional dynamic logic with 'signals' and 'clock relations' as primitives, and with synchronous execution mechanism for modelling RTESs. Then we propose a sound and relatively complete proof system for CDL to provide the verification support. We show how CDL can be used to capture RTES and verify CCSL specifications by analyzing a simple case study.

A Logical Approach for the Schedulability Analysis of CCSL

“…cDL is partially based on the 'CCSL dynamic logic' (CDL) [17], which can capture and verify a simple CCSL specification Rel of a given system p in the form '[p]Rel' (which means 'all execution traces of p satisfy a clock relation Rel'). However CDL fails in handling the schedule problem of CCSL in the form of ' p ϕ' (introduced in Sect.…”