“…where P1, P2, P3, P4 = four digital input lines, G is universal quantification of the expression. Level_1 top control logic FC1, FC2 NOT, addition FC3, FC4 delay, OR FC5, FC6 multiplexing, subtraction Level_2 PI controller FC12, FC13 multiplication, addition FC14, FC17 FC15, FC16 comparison, multiplication FC7, FC8 multiplexing Level_3 bottom control logic FC9 delay FC10 addition FC11 subtraction [7,8,29,30]. Table 3 summarises the comparison results when implementing the EDG application with an array of N*N functional cells.…”