Emerging Applications of 3D Integration and Approximate Computing in High-Performance Computing Systems: Unique Security Vulnerabilities

Yellu, Pruthvy; Zhang, Zhiming; Monjur, Mohammad Mezanur Rahman; Abeysinghe, Ranuli; Yu, Qiaoyan

doi:10.1109/hpec.2019.8916503

Cited by 6 publications

(2 citation statements)

References 35 publications

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“…(2) The Concealment of HTs Increases. Chiplet-based SoW poses new challenges to hardware security, as mentioned in [21][22][23][24][25][26], where third-party chiplet suppliers can implant a single HT's trigger logic and payload logic into separate chiplets. When the trigger logic in one chiplet is activated, it triggers the malicious payload logic located in another chiplet through the communication channel between chiplets, as shown in Figure 3.…”

Section: Motivationmentioning

confidence: 99%

DHRCA: A Design of Security Architecture Based on Dynamic Heterogeneous Redundant for System on Wafer

Mei,

Zhu,

et al. 2024

IET Information Security

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System on Wafer (SoW) based on chiplets may be implanted with hardware Trojans (HTs) by untrustworthy third-party chiplet vendors. However, traditional HTs protection techniques cannot guarantee complete protection against HTs, which poses a great challenge to the hardware security of SoW. In this paper, we propose a computing architecture based on endogenous security theory—dynamic heterogeneous redundant computing architecture (DHRCA) that can tolerate and detect HTs at runtime. The security of our approach is analyzed by building a generalized stochastic coloring petri net (GSCPN) model of DHRCA. The simulation results based on the GSCPN model show that our method can improve the system security probability to 0.8690 and the system availability probability to 0.9750 in the steady state compared with typical triple-mode redundancy and runtime monitoring methods. Furthermore, the impact of different attack and defense strategies on system security of different methods is simulated and analyzed in this paper.

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Section: Motivationmentioning

confidence: 99%

DHRCA: A Design of Security Architecture Based on Dynamic Heterogeneous Redundant for System on Wafer

Mei,

Zhu,

et al. 2024

IET Information Security

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“…the primary thought toward the rear of coherent locking confusion is that piece of the design is changed with a configurable module on the format degree. In the event that the module isn't initiated via the dressmaker, the chip will now not work as expected [4][5][6][7]. for the term of the set upmanufacture enactment way in a depended-on plan house, the chips might be initiated by means of opening the muddled trademark with a secret key that might be scorched into on-chip wires.…”

Section: Introductionmentioning

confidence: 99%

Cube Stripping Function and Logic Restoration Based Hardware Security

P¹,

Rangarajan²,

Selvi³

2022

ESP-JETA

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Guaranteeing security without compromising the exhibition and adaptability of a gadget is basically an exceptionally difficult endeavor for Researchers and Practitioners Approximate circuits (AxCs) tradeoff computational exactness against upgrades in equipment place, put off, or power consumption. IP center transporters who need to make such circuits need to persuade clients regarding the subsequent guess superior grade. As an answer, underwrite PUF based absolutely confirmation conveying AxCs. the vender makes a surmised IP center by and large with an authentication that demonstrates the estimation fine. The proof endorsement is packaged with the surmised IP center and shipped off to the client. We utilize the PUF reaction to free the element of the chip. The benefactor can authoritatively confirm the guess good of the IP center at a section of the standard computational expense for formal confirmation.

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