Emerging technologies and nanoscale computing fabrics

Abstract

Abstract. This chapter describes a reconfigurable computing architecture based on clusters of regular matrices of fine-grain dynamically reconfigurable cells using double-gate carbon nanotube field effect transistors (DG-CNTFET), which exhibit ambivalence (p-type or n-type behaviour depending on the backgate voltage). Hierarchical function mapping methods suitable for the cluster of matrices structure have been devised, and various benchmark circuits mapped to the architecture. This work shows how circuit and architecture designers can work with emerging technology concepts to examine its suitability for use in computing platforms.

New Optimized Reconfigurable ALU Design Based on DG-CNTFET Nanotechnology

“…Here in Figure 4 there is schematic of reconfigurable 3 functions ALU based on DG-CNTFET transistors. The ALU3F block is constituted of 4 different sub-blocks connected together to constitute a 1-bit full adder [12]. The most used sub-block is the 9T sub-block described in Figure 3 [5], [13].…”

New Optimized Reconfigurable ALU Design Based on DG-CNTFET Nanotechnology

“…Here in Figure 4 there is schematic of reconfigurable 3 functions ALU based on DG-CNTFET transistors. The ALU3F block is constituted of 4 different sub-blocks connected together to constitute a 1-bit full adder [12]. The most used sub-block is the 9T sub-block described in Figure 3 [5], [13].…”