Empirical Equation of Wire Sag Model for Semiconductor Packaging With Numerical and Experimental Verification

Abstract

For the semiconductor packaging industry, the issue of wire sag has not been touched upon because only one single layer of wire bond is constructed along the perimeter of the chip system. Over-sag deflections may not cause any problems. However, driven by the demands for smaller and faster advanced microelectronic devices, modern 3-D and multichip modules have become the solution of choice in delivering higher integration and more multifunctional products to meet consumer needs. For 3-D and multichip packaging, excessive wire sag can lead to wires touching against the lower layer, causing a short-circuit and failure of chip functionality. Therefore, gaining knowledge of wire bond sag theory becomes extremely important for advanced packaging. We propose an empirical model to predict the sag stiffness of a wire bond. The sag stiffness of a wire bond is defined to represent its resistance to the sag drag force occurring during the encapsulation process by the molding flow. A higher sag stiffness of a wire bond gives the premise of less sag deflection, thereby avoiding short-circuiting and/or double wire crosstalk due to the closeness of the top-layer to the bottom-layer wire bonds. The theory of sag regarding semiconductor wire bonding has not been documented, to our knowledge, in the literature. Therefore, to deal with this issue, this paper will primarily focus on the theoretical and numerical analysis of sag deflection of a wire bond. A set of sag experiments is conducted to verify the validity of the sag model hypothesis outlined in the earlier paper. Subsequently, an empirical sag model could be put forward to predict the sag stiffness of a wire bond if the corresponding bond spans, bond heights, and material properties are known. The engineered design of a wire bond can be improved through the use of this sag equation. By making use of the proposed sag model, one can attain not only a first-order estimation of the sag deflection but also omit the tedious procedures of numerical analysis.

Rationally Designing the Trace of Wire Bonder Head for Large-Span-Ratio Wire Bonding in 3D Stacked Packaging

“…The development trend of wire bonding has the following three characteristics: the diameter of wire is continually shrinking towards sub-10 µm when trying to reduce the cost and achieve smaller pitch [15]; an effective pitch of less than 50 µm between bonding pads is the tireless pursuit of packaging industry [16]; the span between the two bonds continuously increases but the wire loop profiles is severely lowered so as to interconnect as many chips as possible in a confined space that is thinner than a standard wafer, the ratio of the distance between the 1st & 2nd bonds and the loop height expected to be larger than 5 [17,18]. In a wire loop, the reasonable distribution of kinks on it not only defines the geometrical shape of the wire loop but also effectively prevents wire sagging and short-circuit defects [19]. Therefore, designing eligible trace of the wire bonder head to form kinks on the wire loops ( Figure 1) becomes significantly crucial in high-density wire bonding packaging nowadays [20][21][22].…”

Comparison of Fundamental Frequency and Sweep Resistance of Different Wire Loops Using Finite Element Model

“…1 However, with a continuous demand for miniaturization and higher performance in the packaging industry, 2 wire loops need to be longer and of a¯ner pitch but such a requirement aggravates the risk of short-circuiting.…”