Empirical Mathematical Model of Microprocessor Sensitivity and Early Prediction to Proton and Neutron Radiation-Induced Soft Errors

Abstract

A mathematical model is described to predict microprocessor fault tolerance under radiation. The model is empirically trained by combining data from simulated faultinjection campaigns, and radiation experiments, both with protons (at the CNA facilities, Seville, Spain) and with neutrons (at the LANSCE Weapons Neutron Research facility at Los Alamos, USA). The sensitivity to soft errors of different blocks of commercial processors is identified to estimate the reliability of a set of programs that had previously been optimized, hardened, or both. The results showed a standard error under 0.1, in the case of the ARM processor, and 0.12, in the case of the MSP430 microcontroller.

Analyzing the Influence of Memory and Workload on the Reliability of GPUs Under Neutron Radiation

“…In [23] the authors tested it using gamma ray photons to assess its suitability for space missions by determining its tolerance to radiation using Total Ionizing Dose (TID). In [24], the authors show that using redundant kernel execution is an effective way of reducing the SDC cross-section of the Jetson Nano when exposed to proton irradiation. They also show that the CPU in the SoC is the main source of the functional interrupts detected.…”

Dependability Measurement with Soft Error Caused Exceptions on the Arm Cortex-A9 CPU

“…With 15 workloads distributed among 8 production technique nodes, the effects of multi-bit upsets on six key hardware components of an ARM Cortex-A9 CPU based on Gem5 micro architecture simulator are investigated [17]. A mathematical approach for predicting microprocessor fault tolerance under radiation is provided [18]. Improved virtual platform frameworks have made soft error assessment of more genuine multicore systems easier [19].…”

Microprocessor Error Diagnosis by Trace Monitoring Under Laser Testing

“…An extended approach is used in [20] to analyze the AVF due Multi-Bit Upsets (MBUs). The recent work [26] proposes to overcome the limitations of AVF combining simulation campaigns with radiation results by means of a mathematical model which provides a reliability figure for the different blocks of the processor. In the case of microprocessors, this kind of approaches can provide incorrect results because the very same observed error can be due to misbehaviors in different parts of the architecture.…”