Emulation-based design errors identification

Castelnuovo, A.; Fin, Alessandro; Fummi, Franco; Sforza, F.

doi:10.1109/dftvs.2002.1173533

Cited by 3 publications

(2 citation statements)

References 19 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Existing simulated FI techniques are based on saboteurs, mutants or simulation command-based approach [1]. SystemC-based FI techniques using emulation approach (such as [8]) is outside the scope of this paper due to our focus on simulated FI approach. In the following, existing simulated FI techniques are described.…”

Section: Existing Fault Injection Techniquesmentioning

confidence: 99%

SystemC-Based Minimum Intrusive Fault Injection Technique with Improved Fault Representation

Shafik¹,

Rosinger²,

Al-Hashimi³

2008

2008 14th IEEE International on-Line Testing Symposium

View full text Add to dashboard Cite

In this paper, we propose a new SystemC-based fault injection technique that has improved fault representation in visible and on-the-fly data and signal registers. The technique is minimum intrusive since it only requires replacing the original data or signal types to fault injection enabler types. We compare the proposed simulation technique with recently reported SystemC-based techniques and show that our technique has fast simulation speed, better fault representation, while maintaining simplicity and minimum intrusion. We demonstrate fault injection capabilities in a behavioural SystemC description of MPEG-2 decoder using proposed technique and show that up to 98.9% fault representation within data and signal registers can be achieved.

show abstract

Section: Existing Fault Injection Techniquesmentioning

confidence: 99%

SystemC-Based Minimum Intrusive Fault Injection Technique with Improved Fault Representation

Shafik¹,

Rosinger²,

Al-Hashimi³

2008

2008 14th IEEE International on-Line Testing Symposium

View full text Add to dashboard Cite

show abstract

“…An application programmable interface (API) for one of the most advanced hardware emulator has been developed [11]. It allows to load the emulator memory board and to sample the DUT primary outputs from the emulator equipment.…”

Section: Hardware Emulator Interfacementioning

confidence: 99%

LAERTE++: An Object Oriented High-Level TPG for SystemC Designs

Fin

Fummi

Languages for System Specification

View full text Add to dashboard Cite

This paper describes Laerte++, a high-level test pattern generator (TPG) for SystemC designs. All necessary features of a high-level TPG (e.g., fault models definition, hierarchical analysis, coverage measurements, etc.) are implemented by exploiting native SystemC characteristics funded on OO principles. The framework robustness and extensibility are guaranteed by an accurate use of software engineering methodologies for the Larte++ classes definition and an extensive use of the Standard Template Library (STL) for data structure definition. Laerte++ allows to set up and run an ex-novo TPG session by adding very few C++ code lines to any SystemC design under test description. The applicability and the efficiency of the presented framework have been confirmed by the analyzed benchmarks.

show abstract

Plataforma de co-emulação de falhas em circuitos integrados.

Sarmiento¹,

Arturo²

View full text Add to dashboard Cite

A platform and a technique to improve stuck-at fault grading efficiency through the use of hardware co-emulation is presented. IC manufacturers are always seeking for new ways to test their devices in order to deliver parts with zero defects to their customers. Scan is a well known technique that attains high fault coverage results with efficiency. Demands for new features motivate the creation of high complex systems with a mixture of analog and digital blocks with a communication interface that is difficult to cover with scan patterns. In addition, the logic that configures the chip for each of the different test modes, some BIST memory interfaces, asynchronous clock dividers or generators, among others, are examples of circuits that are blocked or have few observation/control points during scan. A FPGA basedplatform that uses heterogeneous models to emulate digital, analog and memory blocks for fault grading patterns on complex systems is described. Also introduced in our proposal are four types of models that can be used with FPGAs, and the results of applying our fault co-emulation technique to some benchmark circuits including ISCAS89, ADC, iopads and memory controllers.

show abstract

Emulation-based design errors identification

Cited by 3 publications

References 19 publications

SystemC-Based Minimum Intrusive Fault Injection Technique with Improved Fault Representation

SystemC-Based Minimum Intrusive Fault Injection Technique with Improved Fault Representation

LAERTE++: An Object Oriented High-Level TPG for SystemC Designs

Plataforma de co-emulação de falhas em circuitos integrados.

Contact Info

Product

Resources

About