2010 International Electron Devices Meeting 2010
DOI: 10.1109/iedm.2010.5703344
|View full text |Cite
|
Sign up to set email alerts
|

Enabling 3X nm DRAM: Record low leakage 0.4 nm EOT MIM capacitors with novel stack engineering

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
1

Citation Types

0
30
0

Year Published

2012
2012
2022
2022

Publication Types

Select...
7
1

Relationship

1
7

Authors

Journals

citations
Cited by 19 publications
(30 citation statements)
references
References 1 publication
0
30
0
Order By: Relevance
“…The optimization of the dielectrics stacks for the trenched DRAMs was reported in another study. 33 For the higher voltage regime a bias voltage of 3 V was chosen. This is the highest voltage at which all investigated dielectrics show leakage currents low enough for reliable capacitance measurements.…”
Section: Resultsmentioning
confidence: 99%
“…The optimization of the dielectrics stacks for the trenched DRAMs was reported in another study. 33 For the higher voltage regime a bias voltage of 3 V was chosen. This is the highest voltage at which all investigated dielectrics show leakage currents low enough for reliable capacitance measurements.…”
Section: Resultsmentioning
confidence: 99%
“…20 Recent developments on ALD of STO showed that Sr-rich films have a smaller grain size after annealing resulting in lower leakage current values. 19,21 For these reasons monitoring the stoichiometry and crystallinity of STO films is necessary to tune the processing conditions such that the requirements for the application envisioned are met.…”
mentioning
confidence: 99%
“…13,14 and dielectric properties. [10][11][12][13]18 This example shows the importance of resolving the correct process and temperature window to obtain the desired film properties for the specific application targeted. In recent literature, TEM studies have been published on STO films deposited by ALD and crystallized by rapid thermal annealing (RTA) with the aim of determining the STO microstructure and its relation to electrical properties.…”
mentioning
confidence: 99%
“…[15][16][17] However, Sr-rich layers are to be used in next generation DRAM due to their superior dielectric properties and microstructure leading, amongst others, to lower leakage currents. 10,11 The thermal budget applied during annealing as well as specific parameters such as film composition and thickness are of crucial importance as they determine the crystallization behavior and the consequent final microstructure and electrical properties of the crystallized STO films. Crystallization of the film leads to in-plane and out-of-plane densification of the film.…”
mentioning
confidence: 99%
See 1 more Smart Citation