Enabling Branch-Mispredict Level Parallelism by Selectively Flushing Instructions

High-performance, multi-core processors are the key to accelerating workloads in several application domains. To continue to scale performance at the limit of Moore’s Law and Dennard scaling, software and hardware designers have turned to dynamic solutions that adapt to the needs of applications in a transparent, automatic way. For example, modern hardware improves its performance and power efficiency by changing the hardware configuration, like the frequency and voltage of cores, according to a number of parameters, such as the technology used or the workload running at the time. With this level of dynamism, it is essential to simulate next-generation multi-core processors in a way that can both respond to system changes and accurately determine system performance metrics. Currently, no sampled simulation platform can achieve these goals of dynamic, fast, and accurate simulation of multi-threaded workloads. In this work, we propose a solution that allows for fast, accurate simulation in the presence of both hardware and software dynamism. To accomplish this goal, we present Pac-Sim, a novel sampled simulation methodology for fast, accurate sampled simulation that requires no upfront analysis of the workload. With our proposed methodology, it is now possible to simulate long-running dynamically scheduled multi-threaded programs with significant simulation speedups, even in the presence of dynamic hardware events. We evaluate Pac-Sim using the SPEC CPU2017, NPB, and PARSEC multi-threaded benchmarks with both static and dynamic thread scheduling. The experimental results show that Pac-Sim achieves a very low sampling error of 1.63% and 3.81% on average for statically and dynamically scheduled benchmarks, respectively. Pac-Sim also demonstrates significant simulation speedups as high as 523.5 × (210.3 × on average) for the training input set of SPEC CPU2017 running eight threads.

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Enabling Branch-Mispredict Level Parallelism by Selectively Flushing Instructions

Cited by 4 publications

References 44 publications

Simulating Wrong-Path Instructions in Decoupled Functional-First Simulation

Simulating Wrong-Path Instructions in Decoupled Functional-First Simulation

The Intel Programmable and Integrated Unified Memory Architecture Graph Analytics Processor

Pac-Sim: Simulation of Multi-threaded Workloads using Intelligent, Live Sampling

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