Enabling Dynamic System Integration on Maxeler HLS Platforms

Abstract

High Level Synthesis (HLS) tools enable application domain experts to implement applications and algorithms on FPGAs. The majority of present FPGA applications is following a stream processing model which is almost entirely implemented statically and not exploiting the benefits enabled by partial reconfiguration. In this paper, we propose a generic approach for implementing and using partial reconfiguration through an HLS design flow for Maxeler platforms. Our flow extracts HLS generated HDL code from the Maxeler compilation process in order to implement a static FPGA infrastructure as well as run-time reconfigurable stream processing modules. As a distinct feature, our infrastructure can accommodate multiple partial modules in a pipeline daisy-chained manner, which aligns directly to Maxeler's dataflow programming paradigm. The benefits of the proposed flow are demonstrated by a case study of a dynamically reconfigurable video processing pipeline delivering 6.4GB/s throughput.

Fast flow cloud: A stream dataflow framework for cloud FPGA accelerator overlays at runtime

“…11 Section 6.3 evaluates the synthesis, compilation and reconfiguration time of FCC and three other approaches. 4,6,11 Section 6.4…”

“…Table 4 compares the traditional FPGA synthesis flow by using OpenCL and Maxeler, 4 the partial FPGA reconfiguration, 6 the DSP overlay, 11 and FFC.…”

“…FPGA at 233 MHz. TM-PCI approach uses a Xeon E5-1650 core and a Xilinx VC707 board connected by using a PCIe Gen2 slot, and the FPGA TA B L E 4 Design, compile, and reconfiguration time in four approaches: traditional OpenCL/Maxeler 4 FPGA, Maxeler partial reconfigurable, 6 DSP overlay, 11 and FFC F I G U R E 10 Performance comparison in Gops/s: TM overlay, 7 TM-PCI overlay, 8 and FFC on HARPv2 and AWS F1. Higher is better…”

“…Section 6 shows the improvements in the mapping time, reconfiguration time, and performance achieved by FFC in comparison to other overlay-based tools. [6][7][8][9]11 Section 7 discusses related work on FPGA accelerator frameworks. Finally, Section 8 discusses the main conclusions and future work.…”

“…However, any modification requires the project to be re‐synthesized, and the entire FPGA needs reprogramming. Recently, Kritikakis et al 6 extend Maxeler design strategy by using partial reconfiguration, thus reducing the time required to perform localized modifications in the project.…”