Enabling sub-blocks erase management to boost the performance of 3D NAND flash memory

Chen, Tseng-Yi; Chang, Yuan-Hao; Ho, Chien-Chung; Chen, Shuo-Han

doi:10.1145/2897937.2898018

Cited by 21 publications

(11 citation statements)

References 7 publications

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“…Considering the block size becomes larger in recent 3D NAND flash chips, the page move overhead in the GC process keeps increasing [36]. To improve the system performance by reducing GC overheads and boost the device reliability/lifetime, some studies are proposed to make flash chips supporting "sub-block erase" to cut the page move overhead.…”

Section: Case Study On Sub-block Erase Over 3d-nandmentioning

confidence: 99%

“…To improve the system performance by reducing GC overheads and boost the device reliability/lifetime, some studies are proposed to make flash chips supporting "sub-block erase" to cut the page move overhead. In general, the functionality of sub-block erase is enabled by redundant hardware or software emulated free space as the isolation layer [36][37][38]. This section carries out a case study to check the effectiveness of our proposal in the sub-block erase supported 3D-NAND flash memory.…”

Section: Case Study On Sub-block Erase Over 3d-nandmentioning

confidence: 99%

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Low I/O Intensity-aware Partial GC Scheduling to Reduce Long-tail Latency in SSDs

Sha

Song

et al. 2021

ACM Trans. Archit. Code Optim.

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This article proposes a low I/O intensity-aware scheduling scheme on garbage collection (GC) in SSDs for minimizing the I/O long-tail latency to ensure I/O responsiveness. The basic idea is to assemble partial GC operations by referring to several determinable factors (e.g., I/O characteristics) and dispatch them to be processed together in idle time slots of I/O processing. To this end, it first makes use of Fourier transform to explore the time slots having relative sparse I/O requests for conducting time-consuming GC operations, as the number of affected I/O requests can be limited. After that, it constructs a mathematical model to further figure out the types and quantities of partial GC operations, which are supposed to be dealt with in the explored idle time slots, by taking the factors of I/O intensity, read/write ratio, and the SSD use state into consideration. Through a series of simulation experiments based on several realistic disk traces, we illustrate that the proposed GC scheduling mechanism can noticeably reduce the long-tail latency by between 5.5% and 232.3% at the 99.99th percentile, in contrast to state-of-the-art methods.

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Section: Case Study On Sub-block Erase Over 3d-nandmentioning

confidence: 99%

Section: Case Study On Sub-block Erase Over 3d-nandmentioning

confidence: 99%

Low I/O Intensity-aware Partial GC Scheduling to Reduce Long-tail Latency in SSDs

Sha

Song

et al. 2021

ACM Trans. Archit. Code Optim.

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“…Wu et al 1 propose a distanceaware round robin page allocation scheme for improving the utilization of internal parallelism and thus improving the read performance. There are also works proposed to mitigate the detrimental effects of garbage collection activities, [5][6][7]11 or mitigate the retention error and degraded system performance incurred by the process variation. 3,9,12,13 However, few of these works target on the degraded QoS performance incurred by the OSP in 3D CT-based SSDs.…”

Section: Related Workmentioning

confidence: 99%

“…Some works propose to improve the system I/O performance by enhanced internal parallelism, 1,4 which does not consider the QoS performance. There are also works proposed to improve the QoS performance by revised garbage collection, [5][6][7] or mitigate the impaired storage lifetime incurred by process variation. [8][9][10] Since these works do not take account of the unique feature of OSP technique, there still exists a demanding need to enhance the efficacy when leveraging the OSP operations on 3D SSDs.…”

mentioning

confidence: 99%

Machine learning assisted OSP approach for improved QoS performance on 3D charge‐trap based SSDs

Zhu

et al. 2020

Int J Intell Syst

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Three-dimensional (3D) charge-trap based solid-statedrivers (SSDs) have become an emerging storage solution in recent years. One-shot-programming in 3D charge-trap based SSDs could deliver a maximized system input/output (I/O) throughput at the cost of degraded Quality-of-Service (QoS) performance. This paper proposes reinforcement-learning based one-shotprogramming (RLOSP), a reinforcement learning based approach to improve the QoS performance for 3D charge-trap based SSDs. By learning the I/O patterns of the workload environments as well as the device internal status, the proposed approach could properly choose requests in the device queue, and allocate physical addresses for these requests during one-shotprogramming. In this manner, the storage device could deliver an improved QoS performance. Experimental results reveal that the proposed approach could reduce the worst-case latency at the 99.9th percentile by 37.5%-59.2%, with an optimal system I/O throughput.

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“…In Table 3, ''a'' denotes the degree of cell degradation caused by the erase operation and ''b'' denotes the degree of cell degradation caused by the program operation. In general, ''a'' is 1000 times higher than ''b'' [9], [17]. In other words, the degree of degradation caused by the erase operation is more severe than the degree of degradation caused by the program operation.…”

Section: Performance Comparisonmentioning

confidence: 99%

Schemes for Privacy Data Destruction in a NAND Flash Memory

Ahn

Lee

2019

IEEE Access

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We propose schemes for efficiently destroying privacy data in a NAND flash memory. Generally, even if privacy data is erased from NAND flash memories, there is a high probability that the data will remain in an invalid block. This is a management problem arising from characteristics of a program operation and an erase operation of NAND flash memories. When updating pages or performing a garbage collection, there is a problem that valid data remains in at least one unmapped memory block. Is it possible to impose an obligation to delete privacy data from an existing NAND flash memory? This paper is the answer to this question. We propose a partial overwriting scheme, an SLC programming scheme, and a deletion duty pulse application scheme for invalid pages to effectively address privacy data destruction issues caused by the remaining data. Such privacy data destruction schemes basically utilize at least one state in which data can be written to programmed cells based on a multi-level cell program operation. Our privacy data destruction schemes have advantages in terms of block management as compared with conventional erasing schemes, and are significantly economical in terms of time and cost. The proposed privacy data destruction schemes may be easily applied to many storage devices and data centers using a NAND flash memory.INDEX TERMS NAND flash memory, privacy data, destruction, multi-level cell programming, partial overwriting, SLC programming, deletion duty pulse, garbage collection, data center.

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Enabling sub-blocks erase management to boost the performance of 3D NAND flash memory

Cited by 21 publications

References 7 publications

Low I/O Intensity-aware Partial GC Scheduling to Reduce Long-tail Latency in SSDs

Low I/O Intensity-aware Partial GC Scheduling to Reduce Long-tail Latency in SSDs

Machine learning assisted OSP approach for improved QoS performance on 3D charge‐trap based SSDs

Schemes for Privacy Data Destruction in a NAND Flash Memory

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