Encapsulation of Full Adder Using 180nm CNTFET

Manikkule, Diksha; Jaronde, Pravin W.

doi:10.1109/icetet-sip-1946815.2019.9092017

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Cited by 9 publications

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A Synergistic Integration of IoT, Machine Learning, and Flutter Technology for Precise Crop Management

Chakraborty,

Bhattacharjee,

Ghadge

et al. 2024

Lecture Notes in Networks and Systems

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A Synergistic Integration of IoT, Machine Learning, and Flutter Technology for Precise Crop Management

Chakraborty,

Bhattacharjee,

Ghadge

et al. 2024

Lecture Notes in Networks and Systems

View full text Add to dashboard Cite

Performance Analysis of High Speed and Low Power Binary Adders

Bhati

Sharma

Nag

2022

IOP Conf. Ser.: Mater. Sci. Eng.

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In all the arithmetic operations, addition is one of the most important and initial operations used in most of the mathematical equations. The operation is performed by many adders present in the digital world. These adders give us carries with preferred delay and power. The three main features like structure, logic, and compact circuit layout help design a better adder. This Paper aims to analyse and compare various additions for high-speed, low-power and fast calculation. The various adder designs seen in digital signal processing applications require computationally efficient adding and cumulative operations, so blocks with the required attributes must be carefully selected. Various techniques have been proposed to design efficient adders in terms of performance, low power consumption and area. This work focused on 16-bit implementations of highly optimized area-efficient Ripple Carry Adders (RCA) and Look Ahead Carry Adders (LAC), and carry select Adder. Finally, we can prove that the Carry look ahead Adder is very fast in all existing designs. These processes are simulated and synthesized in all ISE Xilinx 14.7 software.

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