Encryption-Based Secure JTAG

Valea, Emanuele; Silva, Mathieu Da; Flottes, Marie-Lise; Natale, Giorgio Di; Rouzeyre, Bruno

doi:10.1109/ddecs.2019.8724654

Cited by 11 publications

(7 citation statements)

References 9 publications

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“…If we use a dedicated cipher for each bit, the cost increases but we can be sure that the key stream perfectly fits to the segment it belongs to; this, on the other hand, is not so simple if the cryptographic core is centralized. In this case, the fact that the key addition is within the scan chain, and not at its boundaries as in [22], causes a phase shift between the data and the key. If a stream cipher is used, then the phase shift can be easily corrected by a corresponding shift in the key stream provided by the user.…”

Section: B Discussionmentioning

confidence: 99%

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Secure Test with RSNs: Seamless Authenticated Extended Confidentiality

Maistri

Reynaud

Portolan

et al. 2021

2021 19th IEEE International New Circuits and Systems Conference (NEWCAS)

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The testability of electronic devices is of critical importance and it is often supported by IEEE standards. The presence of test structures, on the other hand, paves the way for malicious attackers to access the circuit and extract confidential knowledge such as secret keys or intellectual property. Removing the access to these structures after manufacturing test may prevent security breaches, but this solution is not definitive and excludes the possibility of advanced uses such as online debugging, diagnosis of designs and on-line updates or monitoring. For this reason, it is important to maintain the test infrastructure but to protect it against threats either external (e.g., attackers) or internal (e.g., hardware trojans). This can be achieved through protocols ensuring authentication added to confidentiality capabilities. In the case of Reconfigurable Scan Networks (RSN -IEEE 1687), some solutions currently exist, but are limited to external threats. In this paper, we review the recent state of the art in the domain, and present a novel solution addressing in a comprehensive and low-cost manner authentication and confidentiality, both inside and outside the device.

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Section: B Discussionmentioning

confidence: 99%

“…The use of a stream cipher is confirmed in [22], where the secret key is provided by the user, whereas the IV is generated internally using a True Random Number Generator. This approach ensures that the scheme is robust enough against attacks based on value reuse or collisions.…”

Section: B Confidentiality Of Vectors: a Global Approachmentioning

confidence: 99%

Secure Test with RSNs: Seamless Authenticated Extended Confidentiality

Maistri

Reynaud

Portolan

et al. 2021

2021 19th IEEE International New Circuits and Systems Conference (NEWCAS)

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“…When an encryption-based scheme is implemented, the user needs to encrypt the test data with a secret key before shifting the test data via TDI [18]. After the encrypted test data is sent to the device, it will be decrypted with the secret key.…”

Section: ) Encryption-based Methodsmentioning

confidence: 99%

“…The encryption-based countermeasure decrypts the test data and encrypts the response using a cipher circuit inside a chip [18]. Thus the attacker cannot get the true test response until decrypting with the correct key.…”

Section: F Comparison With Other Workmentioning

confidence: 99%

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A Secure JTAG Wrapper for SoC Testing and Debugging

Lee

Yeh

2022

IEEE Access

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IEEE Std. 1149.1, also known as the Joint Test Access Group (JTAG) standard, provides excellent controllability and observability for ICs and hence is widely used in IC testing, debugging, failure analysis, or even online chip control/monitoring. Unfortunately, it has also become a backdoor for attackers to manipulate the ICs or grab confidential information from the ICs. One way to address this problem is to disable JTAG pins after manufacturing testing. However this countermeasure prohibits the in-filed testing and debugging capability. Other countermeasures such as authentication and encryption/decryption methods based on specific static keys have also been proposed. However, these approaches may suffer from side-channel or memory attacks that may figure out the specific keys. This paper presents an authenticationbased secure JTAG wrapper with a dynamic feature to defend against the attacks mentioned above. We generate different keys for different test data dynamically. Therefore, only legal test data can be updated to the test data registers (TDRs) through JTAG. Furthermore, the attackers will get fake responses if they shift in illegal test data, which makes it extremely difficult to break our proposed method. We can also employ the physical unclonable function (PUF) to distinguish the legal test data for different chips. Experiments on a RISC-V CPU processor called SCR1 show that our proposed method can have an area overhead of only 0.49%. INDEX TERMSHardware security, IEEE test standard security, JTAG security, memory attack, secure JTAG wrapper, physical unclonable function (PUF), in-field testing, in-field debugging. SHIH-CHUN YEH received the B.S. degree in electrical engineering from the National Chung Cheng University, Chiayi, Taiwan, in 2019. He is currently pursuing the M.S. degree in electrical engineering from the National Cheng Kung University, Tainan, Taiwan. His current research interests include hardware security, security of IEEE test standards, and security of testing.

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