End-to-End Integration of a Multi-die Glass Interposer for System Scaling Applications

Hedrick, Brittany; Sukumaran, Vijay; Fasano, Benjamin; Tessler, Christopher L.; Garant, J.; Lubguban, Jorge; Knickerbocker, S.; Cranmer, Michael; Ramachandran, Koushik; Melville, Ian; Berger, Daniel; Angyal, M.; Indyk, Richard; Lewison, David; Arvin, Charles; Guerin, Luc; Cournoyer, Maryse; Ouellet, Marc; Audet, Jean; Baez, Franklin; Li, Shidong; Iyer, Subramanian S.

doi:10.1109/ectc.2016.261

Cited by 9 publications

(1 citation statement)

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“…A fundamental limitation of classical on-chip integration is, however, the lack of heterogeneity -all circuits on the chip are fabricated using the same technology, process, and materials. This notion yields an opportunity to leverage non-traditional chip-level heterogeneous integration technologies, such as three-dimensional (3-D) ICs [1], wafer-scale integration (e.g., silicon interconnect fabric [2]), flexible hybrid electronics [3], silicon and glass interposers [4], [5], and others, for next-generation applications. These fine-feature technologies support integration of multiple ICs in high proximity in the horizontal, vertical, or both dimensions, leading to a significant reduction in the latency and energy of inter-die communication.…”

Section: Introductionmentioning

confidence: 99%

Power Delivery for Silicon Interconnect Fabric

Safari

Vaisband

2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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Silicon interconnect fabric (Si-IF) is a wafer-scale heterogeneous integration platform. This platform promotes a paradigm shift in system integration and packaging methods, providing a single hierarchy of integration between the dies and the platform. The Si-IF effectively replaces the interposer, package, and printed circuit board. A power delivery methodology for high power wafer-scale systems (expected to dissipate up to 50 kW of power) is proposed in this paper. The proposed methodology includes three distinct power distribution topologies that are compared in terms of power loss, thermal consideration, and manufacturability. Compatible applications for each topology are also discussed. The electrical model, IR drop, and Ldi/dt noise, of each power distribution topology, are extracted and compared. Assuming a load voltage of 1 V, the three topologies exhibit a total voltage drop of, respectively, 16.68 mV, 9.62 mV, and 12.28 mV, corresponding to, respectively, 1.67%, 0.96%, and 1.23%. Hierarchical integration of decoupling capacitors is also described to ensure low voltage ripple (<5%) at the point of load. The electrical models of the power distribution topologies are verified using FEM and SPICE simulations.

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Section: Introductionmentioning

confidence: 99%