End-to-End Verification of "Equation missing" Processors with ISA-Formal

Reid, Alastair; Chen, Rick; Deligiannis, Anastasios; Gilday, David L.; Hoyes, David; Keen, Will; Pathirane, Ashan; Shepherd, Owen; Vrábel, Peter; Zaidi, Ali H.

doi:10.1007/978-3-319-41540-6_3

Cited by 48 publications

(34 citation statements)

References 15 publications

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“…The most recent report of mainstream commercial use of formal analysis techniques to verify processor designs described how pipeline control verification was done using bounded model checking on ARM processors [26]; the formal verification framework here could also make use of data-path verification results obtained using other formal techniques. This work is impressive, but both its focus and approach are different from ours.…”

Section: Related Workmentioning

confidence: 99%

Verifying x86 instruction implementations

Goel¹,

Slobodová²,

Sumners³

et al. 2020

Proceedings of the 9th ACM SIGPLAN International Conference on Certified Programs and Proofs

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Verification of modern microprocessors is a complex task that requires a substantial allocation of resources. Despite significant progress in formal verification, the goal of complete verification of an industrial design has not been achieved. In this paper, we describe a current contribution of formal methods to the validation of modern x86 microprocessors at Centaur Technology. We focus on proving correctness of instruction implementations, which includes the decoding of an instruction, its translation into a sequence of micro-operations, any subsequent execution of traps to microcode ROM, and the implementation of these micro-operations in execution units. All these tasks are performed within one verification framework, which includes a theorem prover, a verified symbolic simulator, and SAT solvers. We describe the work of defining the needed formal models for both the architecture and micro-architecture in this framework, as well as tools for decomposing the requisite properties into smaller lemmas which can be automatically checked. We additionally cover the advantages and limitations of our approach. To our knowledge, there are no similar results in the verification of implementations of an x86 microprocessor.

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Section: Related Workmentioning

confidence: 99%

Verifying x86 instruction implementations

Goel¹,

Slobodová²,

Sumners³

et al. 2020

Proceedings of the 9th ACM SIGPLAN International Conference on Certified Programs and Proofs

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“…Although proving properties about the hardware implementation is left for future work, the developed infrastructure provides a way to generate testsuites for the processing core from the formal semantics of REDFIN instructions. Furthermore, one can use the semantics to generate parts of the hardware implementation [20] or synthesise efficient instruction subsets [17].…”

Section: Uniform Development Testing and Verification Environmentmentioning

confidence: 99%

“…This is motivated by the cost of precise proof assistant formalisations in terms of human resources: automated techniques are more CPU-intensive, but cause less "human-scaling issues" (Reid at al. [20]). Our goal was to create a framework that could be seamlessly integrated into an existing spacecraft engineering workflow, therefore it needed to have as much proof automation as possible.…”

Section: Related Workmentioning

confidence: 99%

Formal verification of spacecraft control programs (experience report)

Mokhov

Lukyanov

Lechner³

2019

Proceedings of the 12th ACM SIGPLAN International Symposium on Haskell

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Verification of functional correctness of control programs is an essential task for the development of space electronics; it is difficult and time-consuming and typically outweighs design and programming tasks in terms of development hours. We present a verification approach designed to help spacecraft engineers reduce the effort required for formal verification of low-level control programs executed on custom hardware. The approach uses a metalanguage to describe the semantics of a program as a state transformer, which can be compiled to multiple targets for testing, formal verification, and code generation. The metalanguage itself is embedded in a strongly-typed host language (Haskell), providing a way to prove program properties at the type level, which can shorten the feedback loop and further increase the productivity of engineers.The verification approach is demonstrated on an industrial case study. We present REDFIN, a processing core used in space missions, and its formal semantics expressed using the proposed metalanguage, followed by a detailed example of verification of a simple control program.

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“…Better understanding of ISAs and memory models (e.g. [19,46]) are also key to prove the correctness of code operating on low-level devices. Practical and scalable methods for proving the correctness of distributed and/or concurrent systems remains an open problem.…”

Section: Continuous Formal Verificationmentioning

confidence: 99%