Endurance-Aware Flash-Cache Management for Storage Servers

Suei, Pei-Lun; Yeh, Mi-Yen; Kuo, Tei-Wei

doi:10.1109/tc.2013.119

Cited by 9 publications

(5 citation statements)

References 17 publications

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“…As for data analytics, more memory is needed, so we deploy it on a more powerful machine with two Intel Xeon E5620 processors, 32GB RAM and 1TB SAS Seagate disk. Table 2 lists the detailed parameter configuration used in the following experiments, among which the values of DiskRead, DiskWrite, SSDRead, SSDWrite are also used in work [11]. HashTime are based on the realistic test results on our hardware platform (the first one described above).…”

Section: Discussionmentioning

confidence: 99%

“…To improve the flash cache endurance, Pei et al presented a scalable set-associative flash-cache management design in [11], and this management scheme was demonstrated better than traditional N-way set-associative method. In addition, Liang et al [13] attempted to combine phase change memory (PCM) and flash memory to construct a hybrid nonvolatile disk cache for good disk I/O performance and better cache endurance.…”

Section: A Flash Cache Architecturementioning

confidence: 99%

“…And a lot of research work has been done to improve the performance of flash cache from several aspects, e.g. cache organization [9,10,11], cache replacement algorithm [14], flash memory endurance [15], and data consistency [16].…”

Section: Introductionmentioning

confidence: 99%

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DASH: A duplication-aware flash cache architecture in virtualization environment

Chen

Yang

et al. 2014

2014 20th IEEE International Conference on Parallel and Distributed Systems (ICPADS)

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With the rapid development of multi-core and multi-threading technologies, the performance gap between CPU and storage system is widening year by year, causing the storage system to be the bottleneck of the whole system performance. To alleviate this situation, flash memory has been used as the caching device of HDDs. On the other hand, cloud computing is becoming more and more popular and mature in industry field. As the key building block of it, virtualization technology allows several virtual machines (VMs) running on one single physical machine simultaneously, most of which usually run the same or similar operating systems and applications. In this scenario, flash cache will be occupied by many duplicate data blocks. However, existing flash cache architectures and replacement policies don't take this observation into consideration, which greatly limits the efficient use of the flash cache.In this paper, we propose a new duplication-aware flash cache architecture (DASH). In this architecture, flash cache is organized to cache only one copy of the duplicate data blocks, which can notably expand the effective cache capacity, making more I/O requests hit in the cache. Moreover, this architecture can reduce the amount of data written to flash cache, and thus the life span of flash device can be significantly prolonged. Experiments based on realistic applications show that, in some situations, our cache architecture can improve the cache hit ratio by 5 times, reduce the average I/O latency by 63% and eliminate flash cache writes by 81%.

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Section: Discussionmentioning

confidence: 99%

Section: A Flash Cache Architecturementioning

confidence: 99%

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DASH: A duplication-aware flash cache architecture in virtualization environment

Chen

Yang

et al. 2014

2014 20th IEEE International Conference on Parallel and Distributed Systems (ICPADS)

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“…In terms of the management strategies regarding application issues in CPUs, a subblock-based cache management policy addressing high write energy consumption and durability was proposed by Kim et al [25]. Suei et al presented a scalable set-associated flash cache manager to enhance cache durability with fast cache response time and low hit ratio [26]. Wang et al put forward a novel cache management strategy that reduces inter-group write variations and improves the lifetime, to address unbalanced cache write traffic for NVMs technology [27].…”

Section: Related Workmentioning

confidence: 99%

Exploration and optimization of novel replacement and prefetching strategies for inefficiencies of advanced MRAM-based hybrid cache systems

Han,

Jiang

2024

Semicond. Sci. Technol.

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With the emergence of cutting-edge hardware systems such as cloud computing, edge computing, and on-chip neural network accelerators, how to design advanced memory strategies to substitute the traditional ones for maximizing the potential performance of non-volatile memory (NVM) under the existing hardware conditions, has become an urgent research issue for both academia and industrial communities. It is promising and innovative to improve computer systems in the layer of data exchanging with the emerging advanced semiconductor devices. In the paper, to address the inefficiencies of write-intensive, high power consumption, low hit rate and so on, which exist in hybrid Magnetic Random Access Memory (MRAM) cache systems, three novel cache replacement strategies and two cache prefetching strategies are put forward. The proposed triple novel replacement strategies, including historical frequency and time judgments, duplicate data-aware deletion, and dynamic relevance factors computing, can be utilized to compensate for the shortcomings of the traditional Least Recently Used (LRU) replacement strategy, respectively. In the two novel prefetching strategies, region distribution parameters and Listnet ranking network are imported into the caching process, respectively, to achieve optimized hitting performance. The simulation results demonstrate that the proposed replacement strategies can achieve up to 61.76%, 84.91%, 56.49%, and 53.21% optimization of write count, hit rate, dynamic power, and IPC compared to the conventional one. The proposed prefetching strategy can achieve up to 91.27%, 49.25% hit rate and IPC optimization. Meanwhile, the synthetic evaluation of the replacement and prefetching strategies are elaborated in the paper, including multi-core characteristics, information entropy, interplays and the performance constraints between replacement and prefetching mechanism, which would facilitate more credible ideas for future memory inefficiencies management and strategy design.

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“…Suei, Yeh, and Kuo [96] propose a cache design for storage clusters using an SSD as cache for an HDD. Their design focuses on wear-awareness, response time and hit ratio.…”

Section: Caching and Prefetchingmentioning

confidence: 99%

A Checkpoint of Research on Parallel I/O for High-Performance Computing

et al. 2018

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We present a comprehensive survey on parallel I/O in the high performance computing (HPC) context. This is an important field for HPC because of the historic gap between processing power and storage latencies, which causes applications performance to be impaired when accessing or generating large amounts of data. As the available processing power and amount of data increase, I/O remains a central issue for the scientific community. In this survey, we focus on a traditional I/O stack, with a POSIX parallel file system. We present background concepts everyone could benefit from. Moreover, through the comprehensive study of publications from the most important conferences and journals in a five-year time window, we discuss the state of the art of I/O optimization approaches, access pattern extraction techniques, and performance modeling, in addition to general aspects of parallel I/O research. Through this approach, we aim at identifying the general characteristics of the field and the main current and future research topics.

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Endurance-Aware Flash-Cache Management for Storage Servers

Cited by 9 publications

References 17 publications

DASH: A duplication-aware flash cache architecture in virtualization environment

DASH: A duplication-aware flash cache architecture in virtualization environment

Exploration and optimization of novel replacement and prefetching strategies for inefficiencies of advanced MRAM-based hybrid cache systems

A Checkpoint of Research on Parallel I/O for High-Performance Computing

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