Energy- and Area-Efficient Spin–Orbit Torque Nonvolatile Flip-Flop for Power Gating Architecture

Ali, Karim; Li, Fēi; Lua, S. Y. H.; Heng, Chun-Huat

doi:10.1109/tvlsi.2017.2787664

Cited by 28 publications

(28 citation statements)

References 24 publications

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“…At present, many proposed spintronic logic designs, e.g., hybrid magnetic device and CMOS flip-flops, heavily rely on CMOS devices, while only a small portion of the functionality is implemented with magnetic devices [9], [10]. This is, in part, due to the difficulty of achieving all necessary logic functions with STT-MTJ or SOT-MTJ devices, which do not contain sufficient information capacity or dynamics to implement intrinsic logic gates.…”

Section: Introductionmentioning

confidence: 99%

Energy and Performance Benchmarking of a Domain Wall-Magnetic Tunnel Junction Multibit Adder

Xiao

Marinella

Bennett

et al. 2019

IEEE J. Explor. Solid-State Comput. Devices Circuits

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The domain-wall (DW)-magnetic tunnel junction (MTJ) device implements universal Boolean logic in a manner that is naturally compact and cascadable. However, an evaluation of the energy efficiency of this emerging technology for standard logic applications is still lacking. In this article, we use a previously developed compact model to construct and benchmark a 32-bit adder entirely from DW-MTJ devices that communicates with DW-MTJ registers. The results of this large-scale design and simulation indicate that while the energy cost of systems driven by spin-transfer torque (STT) DW motion is significantly higher than previously predicted, the same concept using spin-orbit torque (SOT) switching benefits from an improvement in the energy per operation by multiple orders of magnitude, attaining competitive energy values relative to a comparable CMOS subprocessor component. This result clarifies the path toward practical implementations of an all-magnetic processor system. INDEX TERMS Benchmarking, domain wall (DW), magnetic logic, magnetic tunnel junction (MTJ), post-CMOS logic, spintronics.

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Section: Introductionmentioning

confidence: 99%

Energy and Performance Benchmarking of a Domain Wall-Magnetic Tunnel Junction Multibit Adder

Xiao

Marinella

Bennett

et al. 2019

IEEE J. Explor. Solid-State Comput. Devices Circuits

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“…The cell level analyses are done based on a 2 Â 2 memory array. The simulations run over Cadence Virtuoso and using the SOT-MTJ Verilog-A model demonstrated in [25] and the parameters in Table 1. The system-level analyses are done using the non-volatile memory simulator, known as NVSim [26].…”

Section: Discussionmentioning

confidence: 99%

Area-Efficient Spin-Orbit Torque Magnetic Random-Access Memory

Ali¹

2020

Integrated Circuits/Microchips

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Spin-orbit torque magnetic random-access memory (SOT-MRAM) has shown promising potential to realize reliable, high-speed and energy-efficient on-chip memory. However, conventional SOT-MRAM requires two access transistors per cell. This limits the use of conventional SOT-MRAM in high-density memories. Thus, various architectures in the literature have been proposed to improve the area efficiency of the SOT-MRAM. In this chapter, these proposals are divided into two categories: non-diode-based SOT-MRAM and diode-based SOT-MRAM cells. The non-diode-based proposals may result in a 1-bit effective area saving up to 50% compared to the conventional SOT-MRAM, whereas the diode-based designs may result in 1-bit effective area-saving of up to 75%. However, the area saving may be accompanied by higher energy and reliability issue penalties. Therefore, here, the various proposals in the literature are presented, highlighting the pros and cons of each design. Moreover, the technology requirements to realize these proposals are discussed. Finally, the various designs are evaluated from both cell and system level perspectives.

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“…2 a shows the schematic diagram of the proposed SOT‐NVFF. With the conventional SOT‐NVFF [2], data‐aware backup signal generator (DBSG) is employed to support data aware backup operation. For NVFF operation, two complementary SOT‐MTJ devices (S and Sb) and the transistors for data backup and restore operations, are added in the slave latch for data retention in power gating mode.…”

Section: Proposed Sot‐mtj‐based Nvffmentioning

confidence: 99%

“…Emerging devices based non‐volatile flip‐flop (NVFF) have been proposed to guarantee data retention in power gating system [1]. However, the data backup energy of NVFF has been reported up to 20× times larger than that of data‐restoring operation [1, 2]. In this Letter, we propose a spin‐orbit torque (SOT) magnetic tunnel junction (MTJ) based NVFF with a data‐aware backup scheme to reduce the data backup energy.…”

Section: Introductionmentioning

confidence: 99%

Low‐energy spin‐orbit torque MTJ‐based non‐volatile flip‐flop with data‐aware backup technique

2019

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Spin‐orbit torque magnetic tunnel junction (MTJ) based non‐volatile flip‐flops (NVFFs) have been introduced to provide zero‐leakage standby state without data loss in power‐gating mode. In this Letter, the data‐aware backup scheme for NVFF, where significant energy can be saved by performing data backup only when the stored data and the current data are different is proprosed. Low‐area backup signal generator is also proposed for the proposed data backup scheme. The simulation results with 65 nm process show 88.7% reduction in backup energy when the stored data and the current data are equal.

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Energy- and Area-Efficient Spin–Orbit Torque Nonvolatile Flip-Flop for Power Gating Architecture

Cited by 28 publications

References 24 publications

Energy and Performance Benchmarking of a Domain Wall-Magnetic Tunnel Junction Multibit Adder

Energy and Performance Benchmarking of a Domain Wall-Magnetic Tunnel Junction Multibit Adder

Area-Efficient Spin-Orbit Torque Magnetic Random-Access Memory

Low‐energy spin‐orbit torque MTJ‐based non‐volatile flip‐flop with data‐aware backup technique

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