Energy-Aware Compiler Optimization for VLIW-DSP Cores

Ma, Yung-Cheng; Liu, Tse-An; Chao, Wen-Shih

doi:10.1007/978-3-642-35473-1_77

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Energy-Aware Register Allocation for VLIW Processors

Stuckmann,

Weißbrich,

Payá-Vayá

2024

J Sign Process Syst

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The efficiency of VLIW processors can be improved by reducing the energy consumption associated with accessing the register-file. This paper presents an energy-aware register allocation approach to reduce the dynamic energy consumption of a scheduled program by using an evolutionary algorithm approach and a register access transition energy model. Additionally, the influence of instruction scheduling on energy-aware register allocation is analyzed. By using the proposed energy-aware compiler backend on synthetic applications with random data in the register-file, the dynamic energy consumption of the total processor core for an exemplary VLIW processor can be reduced by up to $$\varvec{21\%}$$ 21 % compared to a heuristic register allocation. In real-world applications from the domain of hearing aids, energy consumption can be reduced by up to $$\varvec{42.7\%}$$ 42.7 % for single applications, and $$\varvec{17.6\%}$$ 17.6 % average across a range of applications.

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