Energy-aware computation duplication for improving reliability in embedded chip multiprocessors

Abstract

Abstract-Compilers designed for current embedded systems must be capable of addressing multiple constraints such as low power, high performance, small memory footprint and form factor, and high reliability at the same time. In particular, optimizing for one constraint should be performed carefully, considering its impact on other constraints. Recent trends indicate that transient errors are becoming increasingly important in embedded systems. Focusing on an embedded chip multiprocessor and array-intensive applications, this paper demonstrates how reliability against transient errors can be improved without impacting execution time by utilizing idle processors for duplicating some of the computations of the active processors. It also shows how a balance between power savings and reliability improvement can be struck using a metric called the energy-delay-fallibility product. Our experimental results indicate that the "percentage of duplicated computations" is a useful high-level metric for studying the tradeoffs among performance, power, and reliability.

A Quick Introduction to Functional Verification of Array-Intensive Programs

“…A global approach to tackle data locality problem is prescribed in [22] which evaluates all the loop nests in an application to be run in an embedded MPSoC simultaneously and schedules the different constituent modules accordingly for parallel execution. In the context of an embedded chip multiprocessor, the method described in [23] underlines how reliability against transient errors can be enhanced without sacrificing execution time by replicating some of the operations being executed on active processors onto (otherwise) idle processors.…”

System-level design optimization of reliable and low power multiprocessor system-on-chip

“…For example, Nicolaidis proposed a time redundancy based technique using multiple instances of execution upon error detection [3]. Chen et al showed a similar technique employing re-execution by idle processing elements [4] highlighting the advantages of low performance overhead. Information redundancy, suggested by Ejlali et al [5], is also an effective technique.…”

“…Traditionally power-aware fault-tolerant design techniques are carried out considering low power and reliability as two separate objectives as in the case of reported works [4,6,9,10]. For effective design optimization with joint low power and high reliability objectives, further studies are needed to understand reliability of applications, particularly from system-level design perspectives.…”

Reducing the Energy Consumption in Fault-Tolerant Distributed Embedded Systems with Time-Constraint

“…Ejlali et al [14] combine time and information redundancy to tolerate transient faults in DVS-enabled systems such that more slack can be used for DVS. Chen et al [15] use idle time in the schedule to either duplicate tasks or put the processor into a low power mode. The design purpose is to minimize the product of energy, delay and the inverse of the reliability and assume the system has no time-constraint.…”