Energy-aware synthesis of application specific MPSoCs

Abstract

In this paper, we propose a framework for synthesis of application specific MultiProcessor System on Chip (MPSoC) for multimedia applications. Our framework searches for a design with minimum energy consumption under area and period constraints. We simultaneously explore selection of voltagefrequency levels, custom instructions, cache configurations, and task mapping. We propose an optimal algorithm based on prune and search operations to efficiently search the complex design space. We also present a heuristic based on map and customize stages to better handle the exponential complexity of the design space, and rapidly find near-optimal solutions. These algorithms are aided by two estimators that can quickly estimate period and energy consumption of a given design point. Experiments reveal that our framework can reduce energy consumption by 37.9% on an average and 57.1% maximum reduction compared to solutions obtained from a combination of existing techniques.

RewardProfiler: A Reward Based Design Space Profiler on DVFS Enabled MPSoCs

“…We can notice in Eq. 10 that we have not considered the GPU cores at all and the reason being that to execute application on both CPU and GPU cores specialized code or framework 9 is required to identify the part of the code or set of tasks to execute on the GPU or CPU. Now, our RewardProfiler have to execute the application on different number of CPU core configuration with the aforementioned frequency levels and check for the values of different reward (R i ) achieved for every configuration.…”

“…However, before evaluating different reward the user inputs the threshold reward (R t hr eshol d ), which is the minimum value of the reward that is acceptable by the user for a desirable quality of service and is user defined during 8 4 frequency scaling levels are F h , F mh , F ml , F l . 9 Frameworks such as CUDA or OpenCL are required to execute tasks on GPU cores.…”

“…Since, energy efficiency are some of the biggest concerns of embedded computing devices, majority of the state-of-the-art methodologies utilize a combination of the aforementioned mapping policies to increase the energy efficiency of the system, but according to [9] there are five popular methods leading to energy reduction in the system, which includes: 1) Dynamic Power Management (DPM) allows idle processing elements or other idle components of the system to be suspended if required in order to reduce energy consumption [10]. 2) Dynamic Voltage Frequency Scaling (DVFS) allows processors to operate at variable voltage-frequency (v-f ) levels [11].…”