Energy-Aware Task Allocation for Network-on-Chip Based Heterogeneous Multiprocessor Systems

Abstract

Energy-efficiency is becoming one of the most critical issues in embedded system design. In Network-on-Chip (NoC) based heterogeneous Multiprocessor Systems, the energy consumption is influenced dramatically by task allocation schemes. Although various approaches are proposed to allocate tasks in an energy-efficient way, existing work does not well explore the tradeoff between the two major power consumers, namely the processors and network links, resulting in suboptimal mappings from a system point of view. In this paper, we first extend the existing Integer Linear Programming (ILP) formulation to take both processing and communication energy into account. Thereafter, we propose a Simulated Annealing with Timing Adjustment (SA-TA) heuristic to accelerate the optimization process. While the SA-TA algorithm achieves performance very close to the global optimum, significant improvement in computation speed is observed.

Energy and Deadline Constrained Robust Stochastic Static Resource Allocation

“…The use of DVFS to balance performance and energy consumption has been studied widely (e.g., [5,11,15]). In [5], the focus is on minimizing energy consumption, rather than maximizing performance, and considers deterministic rather than stochastic execution times as we do in our work.…”

“…In [5], the focus is on minimizing energy consumption, rather than maximizing performance, and considers deterministic rather than stochastic execution times as we do in our work. DVFS is used to tradeoff between energy consumption and makespan in [11], where the workload consists of precedence-constrained applications represented by a directed acyclic graph (DAG).…”

On the energy-aware partitioning of real-time tasks on homogeneous multi-processor systems

“…Huang et al [8] faced the problem of partitioning a workload with precedence constraints on a multiprocessor system while considering communication costs between processors. Their solution relied on complete search and meta-heuristics.…”

From UML specifications to mapping and scheduling of tasks into a NoC, with reliability considerations

“…The work reported in [18], is aimed to perform mapping in design time for heterogeneous architectures. Both computation and communication assessments are taken into account in the optimization process, which is performed via a simulated annealing algorithm.…”