Energy band alignment of atomic layer deposited HfO2 oxide film on epitaxial (100)Ge, (110)Ge, and (111)Ge layers

Abstract

Articles you may be interested inLow-temperature plasma-enhanced atomic layer deposition of HfO2/Al2O3 nanolaminate structure on Si J. Vac. Sci. Technol. B 33, 01A101 (2015) Crystallographically oriented epitaxial Ge layers were grown on (100), (110), and (111)A GaAs substrates by in situ growth process using two separate molecular beam epitaxy chambers. The band alignment properties of atomic layer hafnium oxide (HfO 2 ) film deposited on crystallographically oriented epitaxial Ge were investigated using x-ray photoelectron spectroscopy (XPS). Valence band offset, DE v values of HfO 2 relative to (100)Ge, (110)Ge, and (111)Ge orientations were 2.8 eV, 2.28 eV, and 2.5 eV, respectively. Using XPS data, variation in valence band offset, DE V ð100ÞGe > DE V ð111ÞGe > DE V ð110ÞGe, was obtained related to Ge orientation. Also, the conduction band offset, DE c relation, DE c ð110ÞGe > DE c ð111ÞGe > DE c ð100ÞGe related to Ge orientations was obtained using the measured bandgap of HfO 2 on each orientation and with the Ge bandgap of 0.67 eV. These band offset parameters for carrier confinement would offer an important guidance to design Ge-based p-and n-channel metal-oxide field-effect transistor for low-power application.

Interfacial band alignment and structural properties of nanoscale TiO2 thin films for integration with epitaxial crystallographic oriented germanium

“…We believe that the pre-cleaning of the epitaxial Ge samples in a NH 4 OH:H 2 O 2 :H 2 O wet etch chemistry along with minimizing the transfer time to the PVD chamber provides a promising method for realizing interfacial oxide-free TiO 2 /Ge heterojunctions. Utilizing a similar pre-clean method, we have recently demonstrated an interfacial oxide-free heterointerface for atomic layer deposited Al 2 O 3 , 38 HfO 2 , 39 and pulse laser deposited BaTiO 3 (Ref. 40) on epitaxial Ge.…”

“…These CBOs are calculated by taking into account the errors associated from the band-gap extrapolation using Prior research on high-j dielectrics have indicated a dependence of substrate orientation on the band-offset at the high-j/ semiconductor interface. 38,39 It has been reported that several other parameters, namely, deposition conditions, crystallinity, interface dipole, and inter-diffusion could be responsible for the discrepancies observed in the band alignment values. 43 Band alignment, in principle, can be tuned by changing the chemical structure of the interface.…”

“…24 and 38) and HfO 2 . 25,39 Interestingly, the low CBOs obtained for the aforementioned TiO 2 /Ge system, irrespective of the Ge crystallographic orientation presents the possibility of employing TiO 2 insulating layer in MIS contact applications to enable low specific resistance ohmic contacts to n-type Ge. This application will find key significance to realize ohmic contacts to Ge in the next generation of Ge FinFETs, where different Ge orientations can be exploited to facilitate mobility enhancement for n-and p-channel devices.…”

“…Utilizing the method described above, the corresponding binding energy difference between the Ge3d CL peak and the VBM E for (111)Ge, respectively, as reported earlier. 39 The thickness of epitaxial Ge for these measurements were $80 nm, which was sufficiently thick for XPS analysis since most of the signal in XPS measurement is from within the first 1-10 nm of the sample thickness. The CL to VBM binding energy difference obtained for the thick-TiO 2 film ðE Tables II-IV, respectively.…”

Quasi-zero lattice mismatch and band alignment of BaTiO3 on epitaxial (110)Ge

“…15,16 Among the new high-j dielectric materials, BaTiO 3 (BTO) directly grown on semiconductors has attracted attention for nonvolatile single transistor memory, 19 to reduce the susbthreshold swing and increase the on-current of a transistor. 20,21 BTO has also been used as a buffer layer for integration of Ge on Si and continues to be of interest for added functionalities on Si or Ge for low-power CMOS logic applications.…”