Energy Consumption Oriented Network-on-Chip Mapping Method

Abstract

In this paper, mapping algorithm has been mainly studied. The main work and contribution have been generalized as follows: Through the research of existing onchip network mapping algorithm and global optimization algorithm, a multi-step mapping algorithm for low-power consumption have been designed, which is combined with the task allocation and the task scheduling. Compared with the traditional mapping algorithm, the algorithm in this paper takes the factors of task scheduling and allocation into account, mapping algorithm has three steps: task scheduling, IP core mapping and data block mapping. The simulation results show that the mapping method in this paper can effectively reduce Network-on-Chip (NoC) power consumption. Index Terms-Mapping Algorithm; Task Scheduling; IP Core Mapping; Data Block Mapping; Network-on-Chip (NoC) I. INTRODUCTION With the improvement of SoC (System-on-Chip), NoC is an intercommunication-based network system implemented on an integrated circuit. As the development of IC technology, SoC based on the traditional bus architecture has been unable to meet the increasing requirement of network communication. As an important technology of NoC, it plays an important role in the performance of the network, such as throughput, delay, fault tolerance and load balance. At present, many research institutions and companies engaged in on-chip network research in which the better-known institutions have Satanford University [1], Princeton University [2], the University of Bologna, KTH [3], the SGS-Thomson semiconductor company, Arteriscompany France Curie University [4], the Royal Swedish Institute of Technology, the Netherlands PHILIP laboratories. Networks on chip has arisen as a solution to the poor wire scaling and increasing complexity of large System on Chip (SoC) design. NoCs aim to replace long shared bus wires with scalable switched networks with higher performance, predictable wiring and better interconnect properties. These networks can be made latency insensitive, simplifying the design of complex systems since communication and computation problems can be treated separately. Although NoCs provide many benefits, they add additional logic complexity to the communication architecture. Power consumption in the communication architecture is a major bottleneck in current design [7] and hence, energy-aware optimizations for NoCs are of primary importance. Several optimization methods have been proposed to reduce energy consumption through application specific customizations. These include: customized router buffer sizing [6]; custom topology generation [12]; adaptive routing [16]; and mapping processing elements to tiles [17]. The applications of NoC can be static or dynamic. Regular topologies such as mesh and torus are often used to overcome such plug-and-play compatibility issues. It has become evident through research that the application specific NoC architecture is superior to regular topologies in terms of power consumption and NoC resources [5]. Regular topologies tend to assume that ...