Energy-Effectiveness of Pre-Execution and Energy-Aware P-Thread Selection

Petric, Vlad; Roth, Aaron

doi:10.1145/1080695.1069997

Cited by 4 publications

(5 citation statements)

References 31 publications

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“…Early studies on MLP extract the instructions necessary for the generation of memory accesses as a thread, and then spawn the thread at a certain point in the program execution to a different context of the processor [12]- [19]. Among these studies, those considering power consumption are, to the best of our knowledge, [16] and [19].…”

Section: Studies Considering Power On Mlp Exploitationmentioning

confidence: 99%

“…Among these studies, those considering power consumption are, to the best of our knowledge, [16] and [19]. In [16], Collins et al focus on delinquent loads, which cause frequent LLC misses, and extract pre-execution instructions related only to these.…”

Section: Studies Considering Power On Mlp Exploitationmentioning

confidence: 99%

“…In [16], Collins et al focus on delinquent loads, which cause frequent LLC misses, and extract pre-execution instructions related only to these. In [19], Petric et al estimate performance benefit and energy consumption analytically, and then select good threads in terms of the performance/energy tradeoff.…”

Section: Studies Considering Power On Mlp Exploitationmentioning

confidence: 99%

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Performance of Dynamic Instruction Window Resizing for a Given Power Budget under DVFS Control

Ando

Shioya

2016

IEICE Trans. Inf. & Syst.

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Hideki ANDO†a) and Ryota SHIOYA †b) , Members SUMMARY Dynamic instruction window resizing (DIWR) is a scheme that effectively exploits both memory-level parallelism and instruction-level parallelism by configuring the instruction window size appropriately for exploiting each parallelism. Although a previous study has shown that the DIWR processor achieves a significant speedup, power consumption has not been explored. The power consumption is increased in DIWR because the instruction window resources are enlarged in memoryintensive phases. If the power consumption exceeds the power budget determined by certain requirements, the DIWR processor must save power and thus, the performance previously presented cannot be achieved. In this paper, we explore to what extent the DIWR processor can achieve improved performance for a given power budget, assuming that dynamic voltage and frequency scaling (DVFS) is introduced as a power saving technique. Evaluation results using the SPEC2006 benchmark programs show that the DIWR processor, even with a constrained power budget, achieves a speedup over the conventional processor over a wide range of given power budgets. At the most important power budget point, i.e., when the power a conventional processor consumes without any power constraint is supplied, DIWR achieves a 16% speedup.

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Section: Studies Considering Power On Mlp Exploitationmentioning

confidence: 99%

Section: Studies Considering Power On Mlp Exploitationmentioning

confidence: 99%

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Performance of Dynamic Instruction Window Resizing for a Given Power Budget under DVFS Control

Ando

Shioya

2016

IEICE Trans. Inf. & Syst.

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“…Most of these schemes extract the instructions necessary for prefetching statically as a thread, and then spawn this thread at a certain point in the program execution to a different context of the processor. An energy-aware thread selection scheme proposed by Petric et al [16] estimates performance benefit and energy consumption analytically, and then selects threads with good performance/energy tradeoff. The disadvantage of these schemes, including Petric's scheme, is that they require a multithreaded environment such as simultaneous multithreading [17] or chip multiprocessors.…”

Section: Related Workmentioning

confidence: 99%

Energy-Efficient Pre-Execution Techniques in Two-Step Physical Register Deallocation

Hyodo

Iwamoto

Ando

2009

IEICE Trans. Inf. & Syst.

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SUMMARYInstruction pre-execution is an effective way to prefetch data. We previously proposed an instruction pre-execution scheme, which we call two-step physical register deallocation (TSD). The TSD realizes pre-execution by exploiting the difference between the amount of instruction-level parallelism available with an unlimited number of physical registers and that available with an actual number of physical registers. Although previous TSD study has successfully improved performance, it still has an inefficient energy consumption. This is because attempts are made for instructions to be pre-executed as much as possible, independently of whether or not they can significantly contribute to load latency reduction, allowing for maximal performance improvement. This paper presents a scheme that improves the energy efficiency of the TSD by preexecuting only those instructions that have great benefit. Our evaluation results using the SPECfp2000 benchmark show that our scheme reduces the dynamic pre-executed instruction count by 76%, compared with the original scheme. This reduction saves 7% energy consumption of the execution core with 2% overhead. Performance degrades by 2%, compared with that of the original scheme, but is still 15% higher than that of the normal processor without the TSD.

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“…Concurrently to our work, Petric and Roth [16] developed an infrastructure for selecting pre-execution (prefetching) threads in an SMT processor. To select threads, they use models that minimize Table 4: Characterizing the optimized TLS4-3i and TLS2-3i chips.…”

Section: Related Workmentioning

confidence: 99%

Thread-Level Speculation on a CMP can be energy efficient

Renau

Strauß

Ceze

et al. 2005

Proceedings of the 19th Annual International Conference on Supercomputing

102

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Chip Multiprocessors (CMP) with Thread-Level Speculation (TLS) have become the subject of intense research. However, TLS is suspected of being too energy inefficient to compete against conventional processors. In this paper, we refute this claim. To do so, we first identify the main sources of dynamic energy consumption in TLS. Then, we present simple energy-saving optimizations that cut the energy cost of TLS by over 60% on average with minimal performance impact. The resulting TLS CMP, populated with four 3-issue cores, speeds-up full SPECint 2000 codes by 1.27 on average, while keeping the fraction of the chip's energy consumption due to TLS to only 20%. Compared to a 6-issue superscalar at the same frequency, the TLS CMP is on average faster, while consuming only 85% of its total on-chip power.

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Energy-Effectiveness of Pre-Execution and Energy-Aware P-Thread Selection

Cited by 4 publications

References 31 publications

Performance of Dynamic Instruction Window Resizing for a Given Power Budget under DVFS Control

Performance of Dynamic Instruction Window Resizing for a Given Power Budget under DVFS Control

Energy-Efficient Pre-Execution Techniques in Two-Step Physical Register Deallocation

Thread-Level Speculation on a CMP can be energy efficient

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