Energy Efficiency Aspects of the AMD Zen 2 Architecture

Memory Performance of AMD EPYC Rome and Intel Cascade Lake SP Server Processors

“…We extend the research with a more in-depth analysis of the memory latencies, validate the bandwidth results with different benchmarks and compare latency and bandwidth results with Rome. While cache and memory performance is influenced by power saving mechanisms [10,28,29], the focus of this paper is on the performance at constant processor frequencies.…”

“…Also, data transfers and cache coherency between L2 caches on the CCX are managed by the shadow tags in the L3. The L3 cache slices use a common L3 frequency, which is generally defined by the highest core frequency of all cores within the CCX [29].…”

“…Compared to first generation Zen processors, these have been widened to match the increased width of SIMD execution. Zen 2 floating point units are able to process 256-bit Advanced Vector Extensions (AVX) instructions in one cycle [2,8], even though this could limit core frequencies in some cases [29]. Load and store queues attached to the AGUs have 44 and 48 entries, respectively, and load data from a 32 KiB L1d cache [2,8].…”

“…Main memory latencies cannot be easily compared between processors, since the specifications of the installed memory DIMMs also contribute to their access time. Moreover, adapting I/O p-states [29] and uncore frequencies [28] lead to more uncertainty. We measure a latency of about 220 cycles (110 ns) for the Rome system, and 200 cycles (80 ns) for CLX.…”

“…In real world workloads, both processors might be able to use turbo frequencies. As demonstrated in [29], the Rome processor might throttle to a lower, not publicly disclosed frequency. Ultimately, the used frequencies, and thus achieved bandwidths, depend on the workload and its distribution across cores and the thermal conditions the systems operate in.…”