Energy-Efficient and Area-Saving Asymmetric Capacitor Switching Scheme for SAR ADCs

Abstract

An asymmetric architecture and energy-efficient capacitor switching scheme for successive approximation register (SAR) analog-to-digital converters (ADC) are proposed. The novel architecture achieves 81.25% reduction in capacitor area over the convention SAR. With the third reference voltage VCM and split-MSB switching procedure, the proposed switching scheme achieves 99.01% less switching energy over the convention SAR. Besides the significant energy saving, this asymmetric capacitor architecture also obtains a good performance in nonlinearity simulation. Based on the Matlab simulation for capacitor mismatch, the maximum differential nonlinearity and maximum integral nonlinearity of the proposed scheme are 0.166LSB and 0.122LSB, respectively.

A study on a new criterion for minimum-energy perfect control in the state-space framework

“…1–8 Modern industry control systems impose restrictions on the control signals due to the existing technological limitations. 9–11 In order to meet the requirements of robustness, a number of techniques are applied in the engineering tasks. 12,13 For instance, an application of various nonsquare parameter/polynomial matrices in the inverse model–based control algorithms, including the minimum variance/perfect control procedure, makes such control laws more robust.…”

Successive Approximation Register Analog-to-Digital Converter (SAR ADC) for Biomedical Applications

“…Te MSB capacitor is arranged as the conventional binary-weighted technique, while the next 9 bits are divided into two-stage subarray capacitors that replace the big-weight capacitors with 7 equal capacitors. Several works have adopted special arrangements for capacitor array technique [54][55][56][57][58][59][60][61]. Te asymmetric capacitors technique [54] is shown in Figure 17, where MSB on the higher side of the capacitor array is removed.…”

“…Several works have adopted special arrangements for capacitor array technique [54][55][56][57][58][59][60][61]. Te asymmetric capacitors technique [54] is shown in Figure 17, where MSB on the higher side of the capacitor array is removed. A diferent implementation technique in [55,56] is achieved by utilizing a capacitance multiplexing technique as presented in Figures 18 and 19, respectively.…”

“…Te frst one is the single-side switching method. In this switching method, the switching variation on one side is utilized after the frst three compensations have been utilized [43,54,55,59].…”