Energy-efficient cache design using variable-strength error-correcting codes

Abstract

Voltage scaling is one of the most effective mechanisms to improve microprocessors" energy efficiency. However, processors cannot operate reliably below a minimum voltage, Vccmin, since hardware structures may fail. Cell failures in large memory arrays (e.g., caches) typically determine Vccmin for the whole processor. We observe that most cache lines exhibit zero or one failures at low voltages. However, a few lines, especially in large caches, exhibit multi-bit failures and increase Vccmin. Previous solutions either significantly reduce cache capacity to enable uniform error correction across all lines, or significantly increase latency and bandwidth overheads when amortizing the cost of error-correcting codes (ECC) over large lines.In this paper, we propose a novel cache architecture that uses variable-strength error-correcting codes (VS-ECC). In the common case, lines with zero or one failures use a simple and fast ECC. A small number of lines with multi-bit failures use a strong multi-bit ECC that requires some additional area and latency. We present a novel dynamic cache characterization mechanism to determine which lines will exhibit multi-bit failures. In particular, we use multi-bit correction to protect a fraction of the cache after switching to low voltage, while dynamically testing the remaining lines for multi-bit failures. Compared to prior multi-bit-correcting proposals, VS-ECC significantly reduces power and energy, avoids significant reductions in cache capacity, incurs little area overhead, and avoids large increases in latency and bandwidth.

Energy balance between voltage-frequency scaling and resilience for linear algebra routines on low-power multicore architectures

“…Hardware support for error detection/correction from operation at lower supply voltage was introduced in [16]. The impact on the memory system was specifically studied in [17,18,19]. In [20] the authors explore the potential energy benefits of reducing the chip's voltage to the safe limit (V min ) at a fixed frequency.…”

Operating SECDED-based caches at ultra-low voltage with FLAIR

“…Probability of bit failure as a function of operating voltage. Bit failure data is derived from prior studies [9], [14], [6], [2]. Note that at the target voltage of 485mv the probability of bit failure is 1 out of 996.…”

“…Several recent papers have proposed architecture-based techniques to improve the reliability of large caches at low operating voltages [1] [2][3] [6] [11] [14] [13]. These techniques allow cache bits to fail, but use additional redundancy, such as multi-bit error correcting codes (ECC) to tolerate high bit failure rates.…”

“…To devise our solution, we exploit the insight that even at ultra low voltages only a very small percentage of cache lines have multi-bit failures [2], [13]. Table I shows the percentage of cache lines that have zero error, one error, or two-or-more errors at the target Vmin of 485mv 1 For our target Vmin, less than 10% of the lines would have more than one-bit error.…”

“…If we can identify such faulty lines, then we can enable low-voltage operation by disabling these lines. A recent study, Variable Strength ECC (VS-ECC) [2], proposed a mechanism to perform runtime testing to characterize the error level of each line and allocate appropriate amount of ECC for each line. Unfortunately, the runtime test runs for a long time (several tens of seconds) and VS-ECC still relies on operating a quarter of the cache with high-strength ECC-4 during the testing phase.…”