Energy-Efficient Design of Processing Element for Convolutional Neural Network

Choi, Yoo-Joo; Bae, Dong Myung; Sim, Jaehyeong; Choi, Seungkyu; Kim, Minhye; Kim, Lee-Sup

doi:10.1109/tcsii.2017.2691771

Cited by 27 publications

(7 citation statements)

References 8 publications

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“…The power consumption is 154.98mW and power efficiency can reach up to 1.084 TOPS/W because of the simple and regular data flow. The power efficiency is better than most of designs except for [19] and [34]. [19] uses lower bitwidth hardware to compute 30% -60% sparse network at lower supply voltage to attain lower area cost or power consumption.…”

Section: F Design Comparisonmentioning

confidence: 99%

“…[19] uses lower bitwidth hardware to compute 30% -60% sparse network at lower supply voltage to attain lower area cost or power consumption. [34] uses an optimized numerical representation for lower bitwidth hardware to achieve lower power consumption.…”

Section: F Design Comparisonmentioning

confidence: 99%

“…Various hardware accelerators have been proposed recently [11][12][13][14][15][16][17][18][19][20][21][22][23][33][34][35][36][37][38]. [11]- [15] minimize the communication traffic by a tiling strategy and internal buffer.…”

Section: Introductionmentioning

confidence: 99%

“…[33] provides near nonblocking communication via reconfigurable links with high bandwidth to support efficient irregular dataflow mapping and provide high utilization of computing units. [34] proposes a low precision design that uses heterogeneous representation and significant bits securing encoding which can exploit the advantage of both efficiency of fixed-point and flexibility of floating-point to optimize their PE architecture and consume less power and area. [35] adopts different combinations of input, weight and output data flow to optimize their design.…”

Section: Introductionmentioning

confidence: 99%

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VWA: Hardware Efficient Vectorwise Accelerator for Convolutional Neural Network

Chang

2020

IEEE Trans. Circuits Syst. I

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Hardware accelerators for convolution neural networks (CNNs) enable real-time applications of artificial intelligence technology. However, most of the existing designs suffer from low hardware utilization or high area cost due to complex dataflow. This paper proposes a hardware efficient vectorwise CNN accelerator that adopts a 3×3 filter optimized systolic array using 1-D broadcast dataflow to generate partial sum. This enables easy reconfiguration for different kinds of kernels with interleaved input or elementwise input dataflow. This simple and regular data flow results in low area cost while attains high hardware utilization. The presented design achieves 99%, 97%, 93.7%, 94% hardware utilization for VGG-16, ResNet-34, GoogLeNet, and Mobilenet, respectively. Hardware implementation with TSMC 40nm technology takes 266.9K NAND gate count and 191KB SRAM to support 168GOPS throughput and consumes only 154.98mW when running at 500MHz operating frequency, which has superior area and power efficiency than other designs.

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Section: F Design Comparisonmentioning

confidence: 99%

Section: F Design Comparisonmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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VWA: Hardware Efficient Vectorwise Accelerator for Convolutional Neural Network

Chang

2020

IEEE Trans. Circuits Syst. I

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“…There are various approaches to optimize the dataflow, such as designing an elaborate dataflow [20][21][22][23][24][25][26][27][28], selecting the best dataflow from several candidates [29][30][31][32], and design space exploration [33][34][35][36][37][38][39][40][41]. In addition, it can significantly reduce storage and communication requirement with low bit representation in the CNNs inference, such as a low precision architecture [42][43][44] for reducing on-chip data access and movement requirement. A fair number of these studies focus on the performance and/or the energy efficiency of the computational components.…”

Section: Introductionmentioning

confidence: 99%

High-efficient MPSoC-based CNNs accelerator with optimized storage and dataflow

et al. 2021

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The convolutional neural networks (CNNs) are widely used in modern AI systems for their superior accuracy but at the cost of high computational complexity, which involve enormous communication bandwidth and storage resources requirement. The computation requirement can be addressed effectively to achieve high throughput by highly parallel compute paradigms of current CNNs accelerators. But the energy consumption still remains high as communication can be more expensive than computation, especially for low power embedded platform. To address this problem, this paper proposes a CNNs accelerator based on a novel storage and dataflow on multi-processor system on chip (MPSoC) platform. By minimizing data access and movement and maximizing data reuse, it can achieve the energy efficient CNNs inference acceleration. The optimization strategies mainly involve four aspects. Firstly, an external memory sharing architecture adopting two-dimensional array storage mode for CPU-FPGA collaborative processing is proposed to achieve high data throughput and low bandwidth requirement for off-chip data transmission. Secondly, the minimized data access and movement on chip are realized by designing a multi-level hierarchical storage architecture. Thirdly, a cyclic data shifting method is proposed to achieve maximized data reuse based on both spatial and temporal. In addition, a bit fusion method based on the 8-bit dynamic fixed-point quantization is adopted to achieve double throughput and computational efficiency of a single DSP. The accelerator proposed in this paper is implemented on Zynq UltraScale + MPSoC ZCU102 evaluation board. By running the benchmark network of VGG16 and Tiny-YOLO on the accelerator, the throughput and the energy efficiency are evaluated. Compared with the current typical accelerators, the proposed accelerator can increase system throughput by up to 41x, single DSP throughput by up to 7.63x, and system energy efficiency by up to 6.3x.

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