Energy efficient fJ/spike LTS e-Neuron using 55-nm node

Abstract

While CMOS technology is currently reaching its limits in power consumption and circuit density, a challenger is emerging from the analogy between biology and silicon. Hardware-based neural networks may drive a new generation of bio-inspired computers by the urge of a hardware solution for real-time applications. This paper redesigns a previous proposed electronic neuron (e-Neuron) in a higher firing rate to reduce the silicon area and highlight a better energy efficiency trade-off. Besides, an innovative schematic is proposed to state an e-Neuron library based on Izhikevichs model of neural firing patterns. Both e-Neuron circuits are designed using 55 nm technology node. Physical design of transistors in weak inversion are discussed to a minimal leakage. Neural firing pattern behaviors are validated by post-layout simulations, demonstrating the spike frequency adaptation and the rebound spikes due to postinhibitory effect in LTS e-Neuron. Presented results suggest that the time to rebound spikes is dependent of the excitation current amplitude. Both e-Neurons have presented a fF/spike energy efficiency and a smaller silicon area in comparison to Izhikevichs library propositions in the literature. CCS CONCEPTS• Hardware → Analog and mixed-signal circuit synthesis; Standard cell libraries; Emerging architectures.

Neuromorphic analog spiking-modulator for audio signal processing

“…This paper extends the work already presented in [13] by proposing: (a) a neuromorphic analog spiking processor (NASP) using both eNeurons in a spiking-modulator architecture; and (b) a varicap-based version for both eNeuron to reduce silicon area. Proposed NASP aims at artificial cochlea applications coding an input-signal amplitude in f spike inspired by DR modulators.…”

“…The authors have focused on the analog-circuit design of the two cortex neuron models, named eNeuron [13]. Both eNeurons are part of the six most fundamental classes of firing patterns observed in the mammalian neocortex [14].…”

“…Proposed NASP aims at artificial cochlea applications coding an input-signal amplitude in f spike inspired by DR modulators. The twooutput spiking-modulated signal in NASP is also capable to estimate the signal derivative sign from f spike variation over time combining both Izhikevich's neuron model proposed in [13]. Post-layout simulations (PLS) are carried out to highlight both eNeuron figure-of-merits, and to ensure lowpower and low-silicon area with varicap-based version.…”

“…In addition, it highlights the principles of weak inversion model of saturated MOS transistors. Section 3 proposes the neuromorphic analog spiking processor implementation and analyses recent works dealing with energy efficient circuits [13] and [18]. The proposed NASP is designed using 55 nm technology node exploring highdensity varicap and low supply voltage ( $ 200 mV).…”

A comparative study between E‐neurons mathematical model and circuit model

“…In order to choose the proper circuit implementation of the neuron, which has more similar voltages to ones shown in Figure 1, different types of implemented state-of-the-art eneurons analysed mathematically [8,10,[15][16][17]. Because AHneuron circuit has two main node voltages which determines the circuit behaviour and two critical differential equations, AH neuron has more compatibility with mathematical modelling of Equations ( 1)-( 3) among all other e-neuron circuit implementations.…”