Energy Efficient Hardware Architecture for Matrix Multiplication

Shanmugakumar, M; Srinivasavarma, Vegesna S. M.; Sk, Noor Mahammad

doi:10.1109/cict51604.2020.9312050

Cited by 1 publication

(2 citation statements)

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“…There are several publications about implementation of matrix multiplication algorithms on various specific FPGAs [33][34][35][36] and by means of specialized architecture for circuits [37,38]. Kamranfar et al [37] depict a configurable linear systolic architecture.…”

Section: Related Workmentioning

confidence: 99%

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An Approach for Matrix Multiplication of 32-Bit Fixed Point Numbers by Means of 16-Bit SIMD Instructions on DSP

2022

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Matrix multiplication is an important operation for many engineering applications. Sometimes new features that include matrix multiplication should be added to existing and even out-of-date embedded platforms. In this paper, an unusual problem is considered: how to implement matrix multiplication of 32-bit signed integers and fixed-point numbers on DSP having SIMD instructions for 16-bit integers only. For examined tasks, matrix size may vary from several tens to two hundred. The proposed mathematical approach for dense rectangular matrix multiplication of 32-bit numbers comprises decomposition of 32-bit matrices to matrices of 16-bit numbers, four matrix multiplications of 16-bit unsigned integers via outer product, and correction of outcome for signed integers and fixed point numbers. Several tricks for performance optimization are analyzed. In addition, ways for block-wise and parallel implementations are described. An implementation of the proposed method by means of 16-bit vector instructions is faster than matrix multiplication using 32-bit scalar instructions and demonstrates performance close to a theoretically achievable limit. The described technique can be generalized for matrix multiplication of n-bit integers and fixed point numbers via handling with matrices of n/2-bit integers. In conclusion, recommendations for practitioners who work on implementation of matrix multiplication for various DSP are presented.

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Section: Related Workmentioning

confidence: 99%

“…Kamranfar et al [37] depict a configurable linear systolic architecture. Shanmugakumar et al [38] describe architecture, which utilizes a carry-save adder tree multiplier for multiplication and a carry-lookahead adder for performing addition at the final stage.…”

Section: Related Workmentioning

confidence: 99%