Energy-efficient hardware/software co-synthesis for a class of applications on reconfigurable SoCs

Ou, Jingzhao; Choi, Seonil; Prasanna, Viktor K.

doi:10.1504/ijes.2005.008811

Cited by 5 publications

(7 citation statements)

References 12 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In [15] a multiprocessor SOPC architecture that can be implemented in partially reconfigurable FPGAs is considered, but the system is represented as a simple linear task graph. The method for the cosynthesis of dynamically reconfigurable systems is presented in [16].…”

Section: Related Workmentioning

confidence: 99%

Co-Synthesis of Dynamically Reconfigurable SOPCs Specified by Conditional Task Graphs

Czarnecki¹,

Deniziak²

2008

TOCSJ

View full text Add to dashboard Cite

Abstract:In this work the co-synthesis method, that optimizes dynamically reconfigurable multiprocessor SOPC system architectures, is presented. The algorithm maximizes speed of a SOPC system, taking into consideration the space constraints of the FPGA. The algorithm starts with the initial solution, where all tasks are assigned to only one general purpose processor module. Next, it produces new solutions using iterative improvement methods. To the best of authors' knowledge, it is the first algorithm that takes into consideration mutually exclusive tasks in optimization of dynamically reconfigurable systems. Such tasks are specified using conditional task graphs. Partially reconfigurable FPGAs enable reuse of the same hardware resources for mutually exclusive tasks. In this way, the area occupied by an embedded system can be decreased and free space may be used for other purposes. It was shown that the presented approach can also increase the performance of a SOPC system.

show abstract

Section: Related Workmentioning

confidence: 99%

Co-Synthesis of Dynamically Reconfigurable SOPCs Specified by Conditional Task Graphs

Czarnecki¹,

Deniziak²

2008

TOCSJ

View full text Add to dashboard Cite

show abstract

“…For example, considering the beamforming algorithm discussed in Section 6.3, the application graph can be described as a linear pipeline. A dynamic programming based algorithm proposed in [6] can be used to find a design with minimum energy dissipation for executing one instance of the application.…”

Section: Fig 1 Domain-specific Modelingmentioning

confidence: 99%

“…Then, the correctness of the designs described in Python classes can be verified by instantiating them with appropriate design parameters, generating corresponding Simulink models, and performing arithmetic level simulation in MATLAB/Simulink. Since the beamforming application can be described as a linear pipeline of kernels, the dynamic programing algorithm proposed in [6] can be applied to find a design for this application so that the energy dissipation for executing one data sample is minimized. First, we create a trellis.…”

Section: System-level Optimization Using Malleable Algorithmsmentioning

confidence: 99%

See 1 more Smart Citation

A Methodology for Energy Efficient FPGA Designs Using Malleable Algorithms

Prasanna

2004

Field Programmable Logic and Application

Self Cite

View full text Add to dashboard Cite

Abstract.A recent trend towards integrating FPGAs with many heterogeneous components, such as memory systems, dedicated multipliers, etc., has made them an attractive option for implementing many embedded systems. Paradoxically, the integration that makes modern FPGAs an attractive computing substrate also makes the development of energy efficient FPGA designs very challenging in practice. This is due to the many alternatives available for implementing a desired functionality and a lack of high-level models of FPGA architectures that can accurately capture the energy dissipation behavior of alternatives. To address these issues, we propose a methodology for energy efficient FPGA designs using malleable algorithms. Malleable algorithms are used to expose the architecture-platform aware specifications of alternate implementations of the desired functionalities. Our methodology consists of three major design steps: domain-specific energy performance modeling, development of malleable algorithms, and system-level optimization. Energy efficient designs are realized through close interaction among these three design steps. To illustrate the proposed design methodology and demonstrate the benefits of designing using malleable algorithms, we present the development of a beamforming application through a highlevel MATLAB/Simulink based FPGA design tool developed by us. By tuning the design knobs exposed by malleable algorithms, the design of the beamforming application identified through system-level optimization achieves up to 30% energy reduction compared with other designs considered in our experiments.

show abstract

“…Although many hardware developers have realized the importance of the issue, and put strong efforts in developing power-efficient devices and energysaving mechanisms, most scientific simulation software is still optimized for runtime performance only [7]. A paradigm change is necessary to meet the challenge of energy-efficient computing.…”

Section: Introductionmentioning

confidence: 99%

A unified energy footprint for simulation software

et al. 2012

View full text Add to dashboard Cite

The focus in High-Performance Computing increasingly turns to energy efficiency. Therefore the pure concentration on floating point operations and runtime performance is no longer sufficient. In terms of hardware, this change of paradigm has already taken place: The GREEN500 list as counterpart to the runtime performance oriented TOP500 list has been established. The new metrics take runtime and energy consumption into account. Nevertheless, all these developments consider hardware only -still an inadequate situation to face the challenges of Energy-Efficient Exascale Computing. The necessity of optimizing simulation software with respect to power and energy draft demands for detailed profiling of the power consumption during the calculations and a norm quantifying the respective efficiency. In this paper we propose a unified energy footprint for simulation software that enables a fast comparison between different models, implementations and hardware configurations, respectively. By way of example we provide the footprints for the tomographic reconstruction code PyHST optimized for CPU and GPU operation as well as the operational numerical weather prediction model COSMO. We then discuss the power and energy profiles and investigate the effects of scaling with respect to hardware resources and simulation parameters. Keywords BenchmarkingThe authors want to thank Peter Schöck, Frederic Hupbauer and Alexander Biewer for their support in employing the measurement setup. Furthermore, thanks go to KIT for funding the project in the framework of a Startup-Project.

show abstract

Energy-efficient hardware/software co-synthesis for a class of applications on reconfigurable SoCs

Cited by 5 publications

References 12 publications

Co-Synthesis of Dynamically Reconfigurable SOPCs Specified by Conditional Task Graphs

Co-Synthesis of Dynamically Reconfigurable SOPCs Specified by Conditional Task Graphs

A Methodology for Energy Efficient FPGA Designs Using Malleable Algorithms

A unified energy footprint for simulation software

Contact Info

Product

Resources

About