Energy-Efficient Partial-Duplication Task Mapping Under Multiple DVFS Schemes

Cui, Minyu; Kritikakou, Angeliki; Mo, Lei; Casseau, Emmanuel

doi:10.1007/s10766-022-00724-7

Cited by 4 publications

(3 citation statements)

References 33 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In [3], a heuristic determines which tasks to be duplicated, removing the need for a recovery task for all tasks. An optimal approach that decides which tasks to duplicate, taking into account reliability and real-time constraints is proposed in [13][14][15]. The main difference between [13,15] and [14] is the task model, i.e., independent tasks are considered in [13,15] while tasks with dependencies are considered in [14].…”

Section: Related Work and Motivationmentioning

confidence: 99%

Near-optimal energy-efficient partial-duplication task mapping of real-time parallel applications

Cui

Kritikakou

et al. 2023

Journal of Systems Architecture

Self Cite

View full text Add to dashboard Cite

Section: Related Work and Motivationmentioning

confidence: 99%

Near-optimal energy-efficient partial-duplication task mapping of real-time parallel applications

Cui

Kritikakou

et al. 2023

Journal of Systems Architecture

Self Cite

View full text Add to dashboard Cite

“…The execution time of task 𝜏 𝑖 , when it is executed at frequency 𝑓 𝑙 on a processor, is given by 𝑒 𝑖 /𝑓 𝑙 . The power consumption of a processor is modeled as the sum of static power 𝑃 𝑠 and dynamic power 𝑃 𝑑 , that is 𝑃 𝑐 = 𝑃 𝑠 + 𝑃 𝑑 [8,11]. The static power and dynamic power, under a given voltage/frequency level (𝑣 𝑙 , 𝑓 𝑙 ), are calculated as 𝑃 𝑠 𝑙 = 𝐶 𝑠 𝑣 𝜌 𝑙 and 𝑃 𝑑 𝑙 = 𝐶 𝑑 𝑓 𝑙 𝑣 2 𝑙 , respectively, where 𝐶 𝑠 , 𝜌 and 𝐶 𝑑 are the constants depending on the type of processor.…”

Section: Nodementioning

confidence: 99%

Energy Optimized Task Mapping for Reliable and Real-Time Networked Systems

Zhou

Kritikakou

et al. 2023

ACM Trans. Sen. Netw.

Self Cite

View full text Add to dashboard Cite

Energy efficiency, real-time response, and data transmission reliability are important objectives during networked systems design. This paper aims to develop an efficient task mapping scheme to balance these important but conflicting objectives. To achieve this goal, tasks are triplicated to enhance reliability and mapped on the wireless nodes of the networked systems with Dynamic Voltage and Frequency Scaling (DVFS) capabilities to reduce energy consumption while still meeting real-time constraints. Our contributions include the mathematical formulation of this task mapping problem as mixed-integer programming that balances node energy consumption, enhancing data reliability, under real-time and energy constraints. Compared with the State-of-the-Art (SoA), a joint-design problem is considered in this paper, where DVFS, task triplication, task allocation, and task scheduling are optimized concurrently. To find the optimal solution, the original problem is linearized, and a decomposition-based method is proposed. The optimality of the proposed method is proved rigorously. Furthermore, a heuristic based on the greedy algorithm is designed to reduce the computation time. The proposed methods are evaluated and compared through a series of simulations. The results show that the proposed triplication-based task mapping method on average achieves 24.84% runtime reduction and 28.62% energy saving compared to the SoA methods.

show abstract

“…This adaptability, achieved through the DVFS method implemented by the fuzzy controller, makes it an optimal approach for optimizing LDPC codec operations. It enables efficient power utilization while maintaining desired performance levels [11].…”

Section: Tanner Graphmentioning

confidence: 99%

Designing A Multi-Frequency Low Power Low-Density Parity Check (LDPC) Encoder with A Dynamic Voltage and Frequency Scaling (DVFS) Approach

2023

IJIES

View full text Add to dashboard Cite

Low density parity check (LDPC) codes are highly regarded for their exceptional error correction capabilities, making them a preferred choice for error correction coding (ECC) in modern communication standards. These codes are implemented in specialized integrated circuits (ICs) that facilitate data transmission. However, the power requirements of complementary metal-oxide-semiconductor (CMOS) circuits, which operate across a wide frequency range, present a significant challenge for future communication systems. To address this challenge, this paper proposes a novel multi-frequency power reduction strategy for LDPC encoders. The strategy utilizes dynamic voltage and frequency scaling (DVFS), a well-established power reduction method in CMOS circuits. By combining DVFS with fuzzy logic control, the system optimizes the voltage supplied to the LDPC encoder, achieving substantial power reduction while maintaining coding efficiency, flexibility, and performance. The proposed approach dynamically adjusts the encoder's voltage levels based on real-time conditions, ensuring efficient power consumption across different frequencies. This innovative strategy aims to overcome the power challenges faced by future communication generations, which have been largely overlooked in previous research efforts. This paper aims to assess the effectiveness of a multi-frequency power reduction strategy for LDPC encoders. Through extensive analysis and evaluations, it demonstrates significant power reduction while maintaining LDPC coding efficiency. These findings contribute to the development of power-efficient LDPC encoder designs, meeting the evolving needs of communication systems. Results reveal the system's performance across different frequency ranges. In the lowfrequency range (1 MHz to 100 MHz), a remarkable 90% power reduction is achieved. In the medium-frequency range (100 MHz to 1 GHz), the reduction is 50%, while in the high-frequency range (1 GHz to 5 GHz), it reaches 20% to 14.5%. Notably, the system operates most effectively in the low and medium frequency range, providing substantial power savings. These results highlight the potential of the multi-frequency power reduction strategy for LDPC encoders in addressing power challenges across different frequencies. The significant power reduction achieved demonstrates its effectiveness and adaptability to varying frequency demands. This contributes to the development of power-efficient LDPC encoder designs, optimizing performance and energy consumption in various communication systems.

show abstract

Energy-Efficient Partial-Duplication Task Mapping Under Multiple DVFS Schemes

Cited by 4 publications

References 33 publications

Near-optimal energy-efficient partial-duplication task mapping of real-time parallel applications

Near-optimal energy-efficient partial-duplication task mapping of real-time parallel applications

Energy Optimized Task Mapping for Reliable and Real-Time Networked Systems

Designing A Multi-Frequency Low Power Low-Density Parity Check (LDPC) Encoder with A Dynamic Voltage and Frequency Scaling (DVFS) Approach

Contact Info

Product

Resources

About