Energy Efficient Run-Time Incremental Mapping for 3-D Networks-on-Chip

Abstract

Abstract3-D Networks-on-Chip (NoC) emerge as a potent solution to address both the interconnection and design complexity problems facing future Multiprocessor System-on-Chips (MPSoCs). Effective run-time mapping on such 3-D NoC-based MPSoCs can be quite challenging, as the arrival order and task graphs of the target applications are typically not known a priori, which can be further complicated by stringent energy requirements for NoC systems. This paper thus presents an energy-aware run-time incremental mapping algorithm (ERIM) for 3-D NoC which can minimize the energy consumption due to the data communications among processor cores, while reducing the fragmentation effect on the incoming applications to be mapped, and simultaneously satisfying the thermal constraints imposed on each incoming application. Specifically, incoming applications are mapped to cuboid tile regions for lower energy consumption of communication and the minimal routing. Fragment tiles due to system fragmentation can be gleaned for better resource utilization. Extensive experiments have been conducted to evaluate the performance of the proposed algorithm ERIM, and the results are compared against the optimal mapping algorithm (branch-and-bound) and two heuristic algorithms (TB and TL). The experiments show that ERIM outperforms TB and TL methods with significant energy saving (more than 10%), much reduced average response time, and improved system utilization.

Bubble budgeting: throughput optimization for dynamic workloads by exploiting dark cores in many core systems

“…The floorplan of each tile in NoC is shown as in Fig. 11, as in [37]. The dimension of the Alpha core is adopted from [?…”

“…The configuration of the network-on-chip is listed in Table 3. The many-core system floorplanning can be found in [37]. The temperature threshold is 60 o C. We compare our approach with the following two runtime thermal-aware mapping algorithms that aim to dark silicon era, (1) DsRem [24], where the cores on/off patterning are identified followed by tasks mapped to active cores, and (2) PAT [22], where a core region including inactive cores is found for each application.…”

An efficient runtime power allocation scheme for many-core systems inspired from auction theory

“…Table 4 lists the mixes of the benchmarks selected from PARSEC and SPLASH-2. The thermal parameters are adopted from [35]. Each tile is composed by a processor core, L2 cache bank, and a router.…”

Energy and performance-aware application mapping for inhomogeneous 3D networks-on-chip

“…The evolution of SoC design to the third dimension offers a lot of opportunities such as integration of inhomogeneous cores which results in several challenges including optimal inhomogeneous NoC topologies, router architectures and application mapping techniques [9], [10], [11], [12], [13]. Various 3D NoC topologies are presented and evaluated in [14], [15], [16], [17] where homogeneous 3D routers are employed in each architecture.…”

“…However, these algorithms have very high computational complexities. Wang et al [46] proposed a mapping algorithm for 3D NoCs based on run-time incremental mapping technique [47]. Here, the algorithm tries to map applications to convex regions while utilizing as many vertical links as possible in the mapping process.…”