Energy Efficient Scientific Computing on FPGAs using OpenCL

Weller, Dennis D.; Oboril, Fabian; Lukarski, Dimitar; Becker, J.; Tahoori, Mehdi B.

doi:10.1145/3020078.3021730

Cited by 41 publications

(27 citation statements)

References 11 publications

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“…ey found FPGAs to be suitable for 5 of the 13 dwarves, but noted that they are difficult to use for nonspecialized designers and emphasized the importance of more abstraction and less customization. Reference [4] demonstrates the suitability of FPGAs, programmed via OpenCL, for implementing partial differential equation (PDE) based scientific models. e same article, however, showing an OpenCL kernel written with differences in syntax and compiler hints for two different FPGA target devices/vendors, supports our contention that OpenCL code is not performance portable.…”

Section: Related Workmentioning

confidence: 99%

“…e use of the KPN abstraction for modelling architectures for FPGAs is not a novel concept (e.g., see [21,22]). e key features of this abstraction, which make it very suitable for use as the underlying model for our IR, are as follows (direct quotes in the list are from [20]): 4 International Journal of Reconfigurable Computing (i) Processes (or nodes) communicate via unbounded first-in first-out (FIFO) queues.…”

Section: Model Of Computation: Kahn Process Networkmentioning

confidence: 99%

See 1 more Smart Citation

Automatic Pipelining and Vectorization of Scientific Code for FPGAs

Nabi

Vanderbauwhede

2019

International Journal of Reconfigurable Computing

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There is a large body of legacy scientific code in use today that could benefit from execution on accelerator devices like GPUs and FPGAs. Manual translation of such legacy code into device-specific parallel code requires significant manual effort and is a major obstacle to wider FPGA adoption. We are developing an automated optimizing compiler TyTra to overcome this obstacle. The TyTra flow aims to compile legacy Fortran code automatically for FPGA-based acceleration, while applying suitable optimizations. We present the flow with a focus on two key optimizations, automatic pipelining and vectorization. Our compiler frontend extracts patterns from legacy Fortran code that can be pipelined and vectorized. The backend first creates fine and coarse-grained pipelines and then automatically vectorizes both the memory access and the datapath based on a cost model, generating an OpenCL-HDL hybrid working solution for FPGA targets on the Amazon cloud. Our results show up to 4.2× performance improvement over baseline OpenCL code.

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Section: Related Workmentioning

confidence: 99%

Section: Model Of Computation: Kahn Process Networkmentioning

confidence: 99%

Automatic Pipelining and Vectorization of Scientific Code for FPGAs

Nabi

Vanderbauwhede

2019

International Journal of Reconfigurable Computing

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“…The synthesis backend which is an off-the-shelf commercial HLS tool, accepts the C/C++ code as input and outputs the optimized LSTM hardware implementation on FPGAs. It is necessary to note that each commercial HLS toolchain requires specific coding style to achieve the best performance, and thus the templates of the primitive operators should be tailored accordingly [29].…”

Section: Model Implementationmentioning

confidence: 99%

C-LSTM

Wang

Ding

et al. 2018

Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

188

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Recently, significant accuracy improvement has been achieved for acoustic recognition systems by increasing the model size of Long Short-Term Memory (LSTM) networks. Unfortunately, the everincreasing size of LSTM model leads to inefficient designs on FPGAs due to the limited on-chip resources. The previous work proposes to use a pruning based compression technique to reduce the model size and thus speedups the inference on FPGAs. However, the random nature of the pruning technique transforms the dense matrices of the model to highly unstructured sparse ones, which leads to unbalanced computation and irregular memory accesses and thus hurts the overall performance and energy efficiency.In contrast, we propose to use a structured compression technique which could not only reduce the LSTM model size but also eliminate the irregularities of computation and memory accesses. This approach employs block-circulant instead of sparse matrices to compress weight matrices and reduces the storage requirement from (k 2 ) to (k). Fast Fourier Transform algorithm is utilized to further accelerate the inference by reducing the computational complexity from (k 2 ) to (klogk). The datapath and activation functions are quantized as 16-bit to improve the resource utilization. More importantly, we propose a comprehensive framework called C-LSTM to automatically optimize and implement a wide range of LSTM variants on FPGAs. According to the experimental results, C-LSTM achieves up to 18.8X and 33.5X gains for performance and energy efficiency compared with the state-of-the-art LSTM implementation under the same experimental setup, and the accuracy degradation is very small.

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“…Many other groups of researchers have been interested in OpenCL programming with FPGAs for HPC applications [12][13][14].…”

Section: Related Workmentioning

confidence: 99%

OpenCL-ready High Speed FPGA Network for Reconfigurable High Performance Computing

Kobayashi

Oobata

Fujita

et al. 2018

Proceedings of the International Conference on High Performance Computing in Asia-Pacific Region

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Field programmable gate arrays (FPGAs) have gained attention in high-performance computing (HPC) research because their computation and communication capabilities have dramatically improved in recent years as a result of improvements to semiconductor integration technologies that depend on Moore's Law. In addition to FPGA performance improvements, OpenCL-based FPGA development toolchains have been developed and offered by FPGA vendors, which reduces the programming effort required as compared to the past. These improvements reveal the possibilities of realizing a concept to enable on-the-fly offloading computation at which CPUs/GPUs perform poorly to FPGAs while performing low-latency data movement. We think that this concept is one of the keys to more improve the performance of modern heterogeneous supercomputers using accelerators like GPUs. In this paper, we propose high-performance inter-FPGA Ethernet communication using OpenCL and Verilog HDL mixed programming in order to demonstrate the feasibility of realizing this concept. OpenCL is used to program application algorithms and data movement control when Verilog HDL is used to implement low-level components for Ethernet communication. Experimental results using ping-pong programs showed that our proposed approach achieves a latency of 0.99 µs and as much as 4.97 GB/s between FPGAs over different nodes, thus confirming that the proposed method is effective at realizing this concept.

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Energy Efficient Scientific Computing on FPGAs using OpenCL

Cited by 41 publications

References 11 publications

Automatic Pipelining and Vectorization of Scientific Code for FPGAs

Automatic Pipelining and Vectorization of Scientific Code for FPGAs

C-LSTM

OpenCL-ready High Speed FPGA Network for Reconfigurable High Performance Computing

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