Energy-efficient signal processing using FPGAs

Abstract

In this paper, we present techniques for energy-efficient design at the algorithm level using FPGAs. We then use these techniques to create energy-efficient designs for two signal processing kernel applications: fast Fourier transform (FFT) and matrix multiplication. We evaluate the performance, in terms of both latency and energy efficiency, of FPGAs in performing these tasks. Using a Xilinx Virtex-II as the target FPGA, we compare the performance of our designs to those from the Xilinx library as well as to conventional algorithms run on the PowerPC core embedded in the Virtex-II Pro and the Texas Instruments TMS320C6415. Our evaluations are done both through estimation based on energy and latency equations and through low-level simulation. For FFT, our designs dissipated an average of 60% less energy than the design from the Xilinx library and 56% less than the DSP. Our designs showed a factor of 10 improvement over the embedded processor. These results provide concrete evidence to substantiate the idea that FPGAs can outperform DSPs and embedded processors in signal processing. Further, they show that FPGAs can achieve this performance while still dissipating less energy than the other two types of devices.

A Methodology for Energy Efficient FPGA Designs Using Malleable Algorithms

“…For example, there are three possible hardware bindings for implementing storage elements on Virtex-II Pro, which are registers, slice based RAMs, and embedded Block RAMs (BRAMs). Our work in [2] shows that registers and slice based RAMs have better energy efficiency for implementing small amount of storage while BRAMs have better energy efficiency for implementing large amount of storage. Another example is that matrix multiplication can be implemented using many architectures including a linear array or a 2-D array.…”

“…Various hardware implementations of these kernels on the target FPGA device are also given. Our goals are: (1) to find appropriate high-level abstractions of the given implementations which enable rapid and accurate energy performance estimation of a design instance; (2) to traverse the design space populated through the high-level abstractions and identify energy efficient design(s).…”

Time and Energy Efficient Matrix Factorization Using FPGAs

“…opU from Step 2 is performed to obtain U 12 are available for opMMS. We have proposed an architecture for this operation [7]. Since there is matrix subtraction after matrix multiplication, additional subtraction logic is added.…”

“…In this section, we summarize the energy efficient design techniques [7] employed in our designs. First, we have chosen a linear array of PEs.…”

“…FPGAs have become an attractive option for implementing digital signal processing applications because of their high processing power and customizability [7]. The inclusion of new features in the FPGA fabric, such as a large number of embedded multipliers, further enhance their suitability.…”