Energy Efficient Speed-Independent 64-bit Fused Multiply-Add Unit

Stepchenkov, Yury; Stepchenkov, D.Yu.; Rogdestvenski, Yury; Shikunov, Yury; Diachenko, Yury

doi:10.1109/eiconrus.2019.8657207

Cited by 10 publications

(1 citation statement)

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“…shows a circuit of an optimized ST pipeline utilized in the Fused Multiply-Add (FMA) project[22]. The logic and register parts implement the pipeline stage.…”

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confidence: 99%

Improvement of the Natural Self-Timed Circuit Tolerance to Short-Term Soft Errors

Stepchenkov¹,

Kamenskih²,

Diachenko³

et al. 2020

Adv. sci. technol. eng. syst. j.

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The paper discusses the features of the implementation and functioning of digital self-timed circuits. They have a naturally high tolerance to short-term single soft errors caused by various factors, such as nuclear particles, radiation, and others. Combinational self-timed circuits using dual-rail coding of signals are naturally immune to 91% of typical soft errors classified in the paper. The remaining critical soft errors are related to the state of the dual-rail signal, opposite to the spacer and forbidden in traditional dual-rail coding of signals. Paper proposes to consider this state as the second spacer and to indicate it as a spacer to increase the self-timed circuit tolerance to soft errors. Together with an improved indication of the self-timed pipeline, this provides masking of 100% of the considered typical soft errors in combinational self-timed circuits. Due to internal feedback, self-timed latches and flip-flops are less protected from soft errors, as are synchronous memory cells. But thanks to their indication and the input and output signals generation discipline, they are also immune to 89% of typical soft errors. Usage of the self-timed latches and flip-flops with dual-rail coding of information outputs increases the tolerance of self-timed latches and flip-flops to soft errors by 2%. Application of the DICE-like approach to circuitry and layout design of sequential self-timed circuits provide an increase in their tolerance to the single soft errors up to the level of 100%.

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“…shows a circuit of an optimized ST pipeline utilized in the Fused Multiply-Add (FMA) project[22]. The logic and register parts implement the pipeline stage.…”

mentioning

confidence: 99%