Energy-Efficient TCAM Search Engine Design Using Priority-Decision in Memory Technology

Tsai, Hung-Pei; Yang, Keng-Hao; Peng, Yin-Chi; Lin, Chien-Chen; Tsao, Ya-Han; Chang, Meng-Fan; Chen, Tien-Fu

doi:10.1109/tvlsi.2016.2624990

Cited by 18 publications

(10 citation statements)

References 20 publications

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“…Segmented ML technique proved to be the best to handle all the performance metrics. Table 2 Performance comparison summary of ML-sensing techniques Precharge high [6,14,15] Current-race scheme [22,33] Precharge free [29][30][31][32] Low swing [11,[34][35][36] Segmented [37][38][39][40][41][42][43][44][45] Sele. precharge [46][47][48]…”

Section: Resultsmentioning

confidence: 99%

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The analogy of matchline sensing techniques for content addressable memory (CAM)

Mishra¹,

Mahendra

Hussain

et al. 2020

IET Computers & Digital Techniques

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Performance of a memory depends on the storage stability, yield and sensing speed. Differential input and the latching time of sense amplifiers are considered as primary performance factors in static random access memory. In a content addressable memory (CAM), the sensing is carried out through the matchline (ML) and the time for evaluation is the key to decide the search speed. The density of CAM is on a rise to accommodate a higher amount of information which increases the power dissipation associated with it. Issues such as the logical threshold variation and lower noise margin between match and mismatch are critical in the operation of a CAM. A good ML sensing technique can reduce the ML power with enhanced evaluation speed. This work provides an analogy of various ML sensing techniques based on their pre-charging, evaluation and performance improvement strategies. Estimation on the power dissipation and evaluation time are made and in-depth analysis on their power-speed-overhead trade-off are carried on 64-bit CAM macros.

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Section: Resultsmentioning

confidence: 99%

“…(i) Pre-charge high ML sensing technique [6,14,15]: a simple yet power hungry approach used by most CAM designers. (ii) Current race sensing [22,33]: a pre-charge low strategy on the ML using a current source.…”

Section: Sensing Techniquesmentioning

confidence: 99%

The analogy of matchline sensing techniques for content addressable memory (CAM)

Mishra¹,

Mahendra

Hussain

et al. 2020

IET Computers & Digital Techniques

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show abstract

“…Next, all elements in the set are sorted by the second coordinate (i.e., the number of child states) in descending order (Line 10). All elements in T are processed one-by-one starting with the largest number of states (Lines [11][12][13][14][15][16][17][18][19][20]. Given that the currently processed element is (s, n), if the number of states in the head part (after adding all child states of state s) does not exceed HSIZE, all child states of state s will be added to the head part (Lines 13-15).…”

Section: Flexible Head-body Matching Algorithmmentioning

confidence: 99%

“…There are two types of pattern matching algorithms: software-based and hardware-based, with the second achieving high matching speed via special-purpose devices such as field programmable gate arrays (FPGAs) [9][10][11][12][13], content addressable memory (CAM) [14,15], and application-specific integrated circuits (ASICs) [16]. However, special-purpose devices are susceptible to scalability issues in terms of pattern set size and/or speed.…”

Section: Introductionmentioning

confidence: 99%

A Flexible Pattern-Matching Algorithm for Network Intrusion Detection Systems Using Multi-Core Processors

Lee

Yang

2017

Algorithms

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Abstract:As part of network security processes, network intrusion detection systems (NIDSs) determine whether incoming packets contain malicious patterns. Pattern matching, the key NIDS component, consumes large amounts of execution time. One of several trends involving general-purpose processors (GPPs) is their use in software-based NIDSs. In this paper, we describe our proposal for an efficient and flexible pattern-matching algorithm for inspecting packet payloads using a head-body finite automaton (HBFA). The proposed algorithm takes advantage of multi-core GPP parallelism and single-instruction multiple-data operations to achieve higher throughput compared to that resulting from traditional deterministic finite automata (DFA) using the Aho-Corasick algorithm. Whereas the head-body matching (HBM) algorithm is based on pre-defined DFA depth value, our HBFA algorithm is based on head size. Experimental results using Snort and ClamAV pattern sets indicate that the proposed algorithm achieves up to 58% higher throughput compared to its HBM counterpart.

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“…TCAM finds its applications as look-up table in networking routers [1,2], as translations-look-aside buffers (TLBs) caches in microprocessors [3,4], as database accelerators in big-data analytics [4,5], as a filter when storing signature patterns in Internet-of-Things [6,7], as Local binary patterns recognition system in image processing and DNA sequence matching [8,9]. However, the dedicated bit comparison circuitry in each native TCAM cell lowers its memory density and the inherent massive parallelism makes native TCAM power hungry and expensive [10][11][12].…”

Section: Introductionmentioning

confidence: 99%

EE-TCAM: An Energy-Efficient SRAM-Based TCAM on FPGA

Ullah

Lee

2018

Electronics

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Ternary content-addressable memories (TCAMs) are used to design high-speed search engines. TCAM is implemented on application-specific integrated circuit (native TCAMs) and field-programmable gate array (FPGA) (static random-access memory (SRAM)-based TCAMs) platforms but both have the drawback of high power consumption. This paper presents a pre-classifier-based architecture for an energy-efficient SRAM-based TCAM. The first classification stage divides the TCAM table into several sub-tables of balanced size. The second SRAM-based implementation stage maps each of the resultant TCAM sub-tables to a separate row of configured SRAM blocks in the architecture. The proposed architecture selectively activates at most one row of SRAM blocks for each incoming TCAM word. Compared with the existing SRAM-based TCAM designs on FPGAs, the proposed design consumes significantly reduced energy as it activates a part of SRAM memory used for lookup rather than the entire SRAM memory as in the previous schemes. We implemented the proposed approach sample designs of size 512 × 36 on Xilinx Virtex-6 FPGA. The experimental results showed that the proposed design achieved at least three times lower power consumption per performance than other SRAM-based TCAM architectures.

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Energy-Efficient TCAM Search Engine Design Using Priority-Decision in Memory Technology

Cited by 18 publications

References 20 publications

The analogy of matchline sensing techniques for content addressable memory (CAM)

The analogy of matchline sensing techniques for content addressable memory (CAM)

A Flexible Pattern-Matching Algorithm for Network Intrusion Detection Systems Using Multi-Core Processors

EE-TCAM: An Energy-Efficient SRAM-Based TCAM on FPGA

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