Energy-Efficient Time-Domain Vector-by-Matrix Multiplier for Neurocomputing and Beyond

Abstract

We propose an extremely energy-e cient mixed-signal approach for performing vector-by-matrix multiplication in a time domain. In such implementation, multi-bit values of the input and output vector elements are represented with time-encoded digital signals, while multi-bit matrix weights are realized with current sources, e.g. transistors biased in subthreshold regime. With our approach, multipliers can be chained together to implement large-scale circuits completely in a time domain. Multiplier operation does not rely on energy-taxing static currents, which are typical for peripheral and input/output conversion circuits of the conventional mixed-signal implementations. As a case study, we have designed a multilayer perceptron, based on two layers of 10 × 10 four-quadrant vectorby-matrix multipliers, in 55-nm process with embedded NOR ash memory technology, which allows for compact implementation of adjustable current sources. Our analysis, based on memory cell measurements, shows that at high computing speed the drain-induced barrier lowering is a major factor limiting multiplier precision to ∼ 6 bit. Post-layout estimates for a conservative 6-bit digital input/output N × N multiplier designed in 55 nm process, including I/O circuitry for converting between digital and time domain representations, show ∼ 7 fJ/Op for N > 200, which can be further lowered well below 1 fJ/Op for more optimal and aggressive design.

Photonic Multiply-Accumulate Operations for Neural Networks

“…Also included are the analog limits for photonic and electronic matrix cores with N = 1024 and 4 bits of precision, from Table I. photonic technology together with integrated III-V lasers to emulate biological spiking behavior. It has been proposed together with the Broadcast-and-Weight networking framework [78], and has also received considerable experimental validation, both in the tunable weight units [105] and the nonlinear processors that communicate using such units [7], [111], [112]. These systems are limited by two primary sources of energy consumption: the quiescent power of the laser and amplifier units (which can be as large as 200 mW), and the static power consumption of the heaters used within each filter bank (which can be as large as 2 mW each).…”

Boosted Race Trees for Low Energy Classification

“…The evaluation here has yet to take advantage of a) the asymmetric nature of the logic level transitions (meaning that only 0 to 1 transitions are performance sensitive), b) the true malleability afforded by the decision tree algorithms and the co-design it enables, and c) the ability of delay and INHIBIT operations to be even more efficiently implemented by less traditional technologies. Lastly, the integration of race logicbased accelerators with other circuits operating purely on the time-domain, such as the recently proposed vector-matrix multiplier presented in [1], is another interesting path for exploration towards the construction of more complicated, energy-efficient machine learning systems.…”

In‐Memory Vector‐Matrix Multiplication in Monolithic Complementary Metal–Oxide–Semiconductor‐Memristor Integrated Circuits: Design Choices, Challenges, and Perspectives

“…c) VMM engine design [94] with 0T1R analog weight network utilizing input pulse duration encoding scheme and its corresponding sensing circuit for amplitude-encoded analog output is shown. d) VMM engine design concept [95] for 1T1R weight network using digital input pulse duration encoding scheme and its corresponding sensing circuit for pulse duration-encoded digital output.…”