Energy estimation for 32-bit microprocessors

Brandolese,; Fornaciari, William; Salice,; Sciuto,

doi:10.1109/hsc.2000.843701

Cited by 9 publications

(12 citation statements)

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“…execution time, dynamic power dissipation, memory, and area requirements, are given in a technology library. These values are either based on previous design experience or on estimation and measurement techniques [Brandolese et al 2000;Fornaciari et al 1999;Li et al 1995;Tiwari et al 1994;Muresan and Gebotys 2001]. The technology library further includes information about the available PEs and CLs, such as price, DVS enable flag, etc.…”

Section: Problem Formulation and Preliminariesmentioning

confidence: 99%

“…Thereby, different tasks (different use of instructions) dissipate different amounts of power on the same PE. In the case of an ARM7TDMI processor the current varies between 5.7 and 18.3mA, depending on the functionality which is carried out [Brandolese et al 2000]. Taking this into account, the assumptions to Lemma 1 and Lemma 2 in [Ishihara and Yasuura 1998], stating that energy consumption is independent from the type of operations and input data and depends only on the supply voltage, have to be rejected.…”

Section: Introduction and Related Workmentioning

confidence: 99%

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Iterative schedule optimization for voltage scalable distributed embedded systems

Schmitz

Al-Hashimi

Eles

2004

ACM Trans. Embed. Comput. Syst.

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We present an iterative schedule optimisation for multi-rate system specifications, mapped onto heterogeneous distributed architectures containing dynamic voltage scalable processing elements (DVS-PEs). To achieve a high degree of energy reduction, we formulate a generalised DVS problem, taking into account the power variations among the executing tasks. An efficient heuristic is presented that identifies optimised supply voltages by not only "simply" exploiting slack time, but under the additional consideration of the power profiles. Thereby, this algorithm minimises the energy dissipation of heterogeneous architectures, including power managed processing elements, effectively. Further, we address the simultaneous schedule optimisation towards timing behaviour and DVS utilisation by integrating the proposed DVS heuristic into a genetic list scheduling approach. We investigate and analyse the possible energy reduction at both steps of the co-synthesis (voltage scaling and scheduling), including the power variations effects. Extensive experiments indicate that the presented work produces solutions with high quality.

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Section: Problem Formulation and Preliminariesmentioning

confidence: 99%

Section: Introduction and Related Workmentioning

confidence: 99%

Iterative schedule optimization for voltage scalable distributed embedded systems

Schmitz

Al-Hashimi

Eles

2004

ACM Trans. Embed. Comput. Syst.

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“…The statistical properties of the residual R Ö Ð Õ and of the chosen estimator are discussed in [5]. By applying the same method used for the single-processor case, the expression for the variance can be derived and results:…”

Section: Assembly-level Modelmentioning

confidence: 99%

“…To derive the currents a learning-set Ë Ä of power-characterized instructions can be used [5]. Defining the matrices IN × Ò × , A × and IF , equation (1) can be rewritten as:…”

Section: Assembly-level Modelmentioning

confidence: 99%

A multi-level strategy for software power estimation

Brandolese¹,

Fornaciari²,

Pomante³

et al.

Proceedings 13th International Symposium on System Synthesis

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“…To capture this effect, we represent each task by a power dissipation factor, Pwr_Factor( ), that can be extracted through profiling and measurement [2] [3].…”

Section: Problem Formulationmentioning

confidence: 99%