Energy minimization in the STT-RAM-based high-capacity last-level caches

Khajekarimi, Elyas; Jamshidi, Kamal; Vafaei, Abbas

doi:10.1007/s11227-019-02918-2

Cited by 2 publications

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“…Spin‐transfer torque RAM (STT‐RAM) as one of these candidates has the advantages of ultra‐low leakage power, small cell size, scalability and non‐volatility [7]. However, its main drawbacks are long write latency and high write energy which hinder its direct use as the on‐chip caches [8, 9]. To alleviate the limitations of one memory technology, an effective strategy is utilising hybrid structure, which exploits the complementary features of different memory technologies [10].…”

Section: Introductionmentioning

confidence: 99%

Integer linear programming model for allocation and migration of data blocks in the STT‐RAM‐based hybrid caches

Khajekarimi

Jamshidi

Vafaei

2020

IET Computers & Digital Techniques

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Spin-transfer torque random access memory (STT-RAM) has emerged as an eminent choice for the larger on-chip caches due to high density, low static power consumption and scalability. However, this technology suffers from long latency and high energy consumption during a write operation. Hybrid caches alleviate these problems by incorporating a write-friendly memory technology such as static random access memory along with STT-RAM technology. The proper allocation of data blocks has a significant effect on both performance and energy consumption in the hybrid cache. In this study, the allocation and migration problem of data blocks in the hybrid cache is examined and then modelled using integer linear programming (ILP) formulations. The authors propose an ILP model with three different objective functions which include minimising access latency, minimising energy and minimising energy-delay product in the hybrid cache. Evaluations confirm that the proposed ILP model obtains better results in terms of energy consumption and performance compared to the existing hybrid cache architecture.

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