Energy parsimonious circuit design through probabilistic pruning

Lingamneni, Avinash; Enz, Christian; Nagel, Jean-Luc; Palem, Krishna V.; Piguet, Christian

doi:10.1109/date.2011.5763130

Cited by 86 publications

(87 citation statements)

References 18 publications

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“…Those results are showing similar performances than in current state-of-the-art pruning techniques [8]. The pruning technique has an average time of execution of 1.5 seconds 1 .…”

Section: B Post-pruning Experimental Resultssupporting

confidence: 62%

“…Thus, inexact circuit proved their operational efficiency when result quality is not purely needed. Commonly used design techniques for inexact circuits prune, i.e., delete components of an exact logic circuit [7], [8]. At every pruning steps, critical components are selected and pruned in order to minimize the output error while maximizing the power reduction.…”

Section: Introductionmentioning

confidence: 99%

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A fast pruning technique for low-power inexact Circuit design

Broc

Gaillardon

Amarù

et al. 2015

2015 IEEE 6th Latin American Symposium on Circuits &Amp; Systems (LASCAS)

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Abstract-Inexact Circuits are circuits in which the accuracy of the output can be traded for cost savings (energy, area and/or delay). In the context of advanced technology scaling and power density increase, inexact circuits appear to be very promising as a solution. In this paper, we present a novel pruning technique developed as a logic level method to select and prune parts of a digital circuit. The error is computed at each pruning step using probabilistic error propagation and Hamming distance computation, making the evaluation possible at runtime. The technique was validated on several parallel adder architectures. Experimental results proved the efficiency of the technique with Energy-Delay-Area product reduction of 1.8× for less than 10 −4 % of relative error on the considered benchmarks at 45-nm technology node. I. INTRODUCTIONIn the context of advanced technology scaling and power density increase, circuit design innovations are required to keep the power budget under control. Inexact or approximate circuit design is a computing solution that trades circuit precision for cost reduction. Cost can be energy, area and/or delay. Approximate solutions are already heavily used in the field of computer science, especially in the multimedia domain where systems can tolerate varying amounts of error and still realize useful computations. For example, the need for exact results is not justified in applications that interact with human perception, such as vision and audition [1]. Thereby, exploiting approximate computing at the hardware level seems to be a relevant solution that can be applied to a range of applications in exchange for a higher energy efficiency.Initial attempts of inexact circuit design focused on manual redesign of common arithmetic building blocks [2] or the use of logic synthesis to generate approximate circuits [3] by selecting portions of a circuit and applying logic simplifications that do not impact more than one circuit output at a time. Other synthesis techniques achieving power reduction are based on selectively stopping the clock in portions of the circuit where active and exact computation is not required [4], or use precomputation based on sequential logic optimization like in [5]. Lately, a concrete chip prototype [6] was developed employing a pruning technique. The chip implements an inexact 64-bit Kogge-Stone adder [6] and demonstrates a cost saving quantified through the Energy-Delay-Area Product (EDAP) of 1.2-1.6× with an acceptable error bound of less than 0.1% of relative error. Thus, inexact circuit proved their operational efficiency when result quality is not purely needed. Commonly used design techniques for inexact circuits prune, i.e., delete components of an exact logic circuit [7], [8]. At every pruning steps, critical components are selected and pruned in order to minimize the output error while maximizing the power reduction. This selection is typically based on two parameters: the significance, which measures the components impact on the output results and the act...

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“…Those results are showing similar performances than in current state-of-the-art pruning techniques [8]. The pruning technique has an average time of execution of 1.5 seconds 1 .…”

Section: B Post-pruning Experimental Resultssupporting

confidence: 62%

Section: Introductionmentioning

confidence: 99%

A fast pruning technique for low-power inexact Circuit design

Broc

Gaillardon

Amarù

et al. 2015

2015 IEEE 6th Latin American Symposium on Circuits &Amp; Systems (LASCAS)

View full text Add to dashboard Cite

show abstract

“…The amount of error is simply proportional to the number of pruned elements. This technique was first introduced in [1], where full adder cells were removed from various adder architectures, resulting in gains of up to 7.5 X in Energy-DelayArea Product (EDAP), for a 10 % relative error magnitude.…”

Section: State-of-the-art a Probabilistic Pruningmentioning

confidence: 99%

Near/Sub-Threshold Circuits and Approximate Computing: The Perfect Combination for Ultra-Low-Power Systems

Schlachter

Camus

Enz

2015

2015 IEEE Computer Society Annual Symposium on VLSI

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Abstract-While sub/near-threshold design offers the minimal power and energy consumption, such approach strongly deteriorates circuit performances and robustness against PVT (process/voltage/temperature) variations, leading to gigantic speed penalties and large silicon areas. Inexact and approximate circuit design can address these issues by trading calculation accuracy for better silicon area, circuit speed and even better power consumption. This paper reviews and proposes improvements for two approximate computing techniques applicable to arithmetic circuits: gate-level pruning and carry speculation. A critical study is then carried out considering several error metrics, and for the first time, those techniques are combined to produce approximate adders showing even higher gains at similar error levels. It is then shown that those techniques can be applied to a sub-threshold library to mitigate the large variability.

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“…For example, in audio and image processing or in wireless communication, it might be desirable to get better performance (faster, smaller, less powerhungry systems) at expenses of some quality degradation. Recently, a few papers have addressed this issue of designing imprecise hardware to save power [1], [2], [3], [4]. In this work, we introduce a systematic way of having imprecise arithmetic operations for the two most common operations: addition and multiplication.…”

Section: Introductionmentioning

confidence: 99%

Imprecise arithmetic for low power image processing

Albicocco

Cardarilli

Nannarelli

et al. 2012

2012 Conference Record of the Forty Sixth Asilomar Conference on Signals, Systems and Computers (ASILOMAR)

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Abstract-Sometimes reducing the precision of a numerical processor, by introducing errors, can lead to significant performance (delay, area and power dissipation) improvements without compromising the overall quality of the processing. In this work, we show how to perform the two basic operations, addition and multiplication, in an imprecise manner by simplifying the hardware implementation. With the proposed "sloppy" operations, we obtain a reduction in delay, area and power dissipation, and the error introduced is still acceptable for applications such as image processing.

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Energy parsimonious circuit design through probabilistic pruning

Cited by 86 publications

References 18 publications

A fast pruning technique for low-power inexact Circuit design

A fast pruning technique for low-power inexact Circuit design

Near/Sub-Threshold Circuits and Approximate Computing: The Perfect Combination for Ultra-Low-Power Systems

Imprecise arithmetic for low power image processing

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